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| Presentation | 2006-01-18 13:55 Over 40-Gbit/s Digital Circuits Using InP HEMT Technology Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Kozo Makiyama, Tsuyoshi Takahashi, Naoki Hara, Tatsuya Hirose (Fujitsu Labs.) Link to ES Tech. Rep. Archives:  ED2005-193 MW2005-147 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we describe ultra high-speed digital ICs operated at 40 Gbit/s. Multiphase architecture we developed makes it possible to achieve 50-Gbit/s full-rate 4:1 MUX with low power consumption of 0.45W. We also developed novel NRZ-RZ converter with retiming function. It operated at 50Gbit/s. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | InP HEMT / Multiplexer / Multiphase clock architecture / NRZ-RZ converter / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 520, ED2005-193, pp. 7-12, Jan. 2006. | |
| Paper # | ED2005-193 | |
| Date of Issue | 2006-01-11 (ED, MW) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ED2005-193 MW2005-147 |
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| Conference Information | |
| Committee | ED MW |
| Conference Date | 2006-01-18 - 2006-01-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Compound Semiconductor IC and High-Speed, High-Frequency Devices |
| Paper Information | |
| Registration To | ED |
| Conference Code | 2006-01-ED-MW |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Over 40-Gbit/s Digital Circuits Using InP HEMT Technology |
| Sub Title (in English) | |
| Keyword(1) | InP HEMT |
| Keyword(2) | Multiplexer |
| Keyword(3) | Multiphase clock architecture |
| Keyword(4) | NRZ-RZ converter |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Toshihide Suzuki |
| 1st Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 2nd Author's Name | Yoichi Kawano |
| 2nd Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 3rd Author's Name | Yasuhiro Nakasha |
| 3rd Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 4th Author's Name | Kozo Makiyama |
| 4th Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 5th Author's Name | Tsuyoshi Takahashi |
| 5th Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 6th Author's Name | Naoki Hara |
| 6th Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
| 7th Author's Name | Tatsuya Hirose |
| 7th Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Labs.) |
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| Speaker | Author-1 |
| Date Time | 2006-01-18 13:55:00 |
| Presentation Time | 25 minutes |
| Registration for | ED |
| Paper # | ED2005-193, MW2005-147 |
| Volume (vol) | vol.105 |
| Number (no) | no.520(ED), no.523(MW) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2006-01-11 (ED, MW) |
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