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Paper Abstract and Keywords
Presentation 2005-12-16 10:50
A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Masafumi Takahashi, Yukihito Oowaki (Toshiba Corp.) Link to ES Tech. Rep. Archives: ICD2005-196
Abstract (in Japanese) (See Japanese page) 
(in English) A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the data transition probability is less than 55%. By employing the conditional clocking flip-flop circuits in a mobile applications LSI, the power consumption is reduced by 8-31%.
Keyword (in Japanese) (See Japanese page) 
(in English) clock gating / flip-flop / low power / / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 476, ICD2005-196, pp. 25-29, Dec. 2005.
Paper # ICD2005-196 
Date of Issue 2005-12-09 (ICD) 
ISSN Print edition: ISSN 0913-5685
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2005-12-15 - 2005-12-16 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2005-12-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI 
Sub Title (in English)  
Keyword(1) clock gating  
Keyword(2) flip-flop  
Keyword(3) low power  
Keyword(4)  
Keyword(5)  
Keyword(6)  
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Keyword(8)  
1st Author's Name Mototsugu Hamada  
1st Author's Affiliation Toshiba Corp. (Toshiba Corp.)
2nd Author's Name Hiroyuki Hara  
2nd Author's Affiliation Toshiba Corp. (Toshiba Corp.)
3rd Author's Name Tetsuya Fujita  
3rd Author's Affiliation Toshiba Corp. (Toshiba Corp.)
4th Author's Name Chen Kong Teh  
4th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
5th Author's Name Takayoshi Shimazawa  
5th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
6th Author's Name Naoyuki Kawabe  
6th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
7th Author's Name Takeshi Kitahara  
7th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
8th Author's Name Yu Kikuchi  
8th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
9th Author's Name Tsuyoshi Nishikawa  
9th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
10th Author's Name Masafumi Takahashi  
10th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
11th Author's Name Yukihito Oowaki  
11th Author's Affiliation Toshiba Corp. (Toshiba Corp.)
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Speaker Author-1 
Date Time 2005-12-16 10:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2005-196 
Volume (vol) vol.105 
Number (no) no.476 
Page pp.25-29 
#Pages
Date of Issue 2005-12-09 (ICD) 


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