Paper Abstract and Keywords |
Presentation |
2005-12-16 10:50
A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Masafumi Takahashi, Yukihito Oowaki (Toshiba Corp.) Link to ES Tech. Rep. Archives: ICD2005-196 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the data transition probability is less than 55%. By employing the conditional clocking flip-flop circuits in a mobile applications LSI, the power consumption is reduced by 8-31%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
clock gating / flip-flop / low power / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 476, ICD2005-196, pp. 25-29, Dec. 2005. |
Paper # |
ICD2005-196 |
Date of Issue |
2005-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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Link to ES Tech. Rep. Archives: ICD2005-196 |
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