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| Paper Abstract and Keywords | ||
| Presentation | 2005-12-02 11:25 A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) Link to ES Tech. Rep. Archives:  ICD2005-175 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each task module of the bus system while satisfying the given end-to-end real-time constraint of the entire system such as throughput and/or latency constraints. In this paper, we define a scenario as execution sequences of tasks and bus transfers executed in a bus system. Then we propose a method to derive real-time constraints for each task and bus transfer from a given bus system configuration (including bus topology) and a scenario. In deriving the real-time constraints, we consider operation strengths of tasks, the amount of bus transfers, and bus scheduling policies (either fixed priority or round robin). We show that our method is effective for a MPEG2 decoder bus system. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Bus systems / Real-time systems / Pipelined processing / Multimedia processing / Cycle budgeting / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, pp. 25-30, Nov. 2005. | |
| Paper # | ||
| Date of Issue | 2005-11-25 (VLD, ICD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-175 |
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| Conference Information | |
| Committee | VLD ICD DC IPSJ-SLDM |
| Conference Date | 2005-11-30 - 2005-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design/Verification/Test of VLSI systems, etc. |
| Paper Information | |
| Registration To | IPSJ-SLDM |
| Conference Code | 2005-11-VLD-ICD-DC-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios |
| Sub Title (in English) | |
| Keyword(1) | Bus systems |
| Keyword(2) | Real-time systems |
| Keyword(3) | Pipelined processing |
| Keyword(4) | Multimedia processing |
| Keyword(5) | Cycle budgeting |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Seiji Yamaguchi |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Tadaaki Tanimoto |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
| 3rd Author's Name | Akio Nakata |
| 3rd Author's Affiliation | Osaka University (Osaka Univ.) |
| 4th Author's Name | Teruo Higashino |
| 4th Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2005-12-02 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | IPSJ-SLDM |
| Paper # | VLD2005-80, ICD2005-175, DC2005-57 |
| Volume (vol) | vol.105 |
| Number (no) | no.443(VLD), no.446(ICD), no.449(DC) |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2005-11-25 (VLD, ICD, DC) |
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