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| Presentation | 2005-12-02 09:30 On Low Capture Power Test Generation for Scan Testing Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) Link to ES Tech. Rep. Archives:  ICD2005-171 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This may cause excessive IR drop, resulting in significant test-induced yield loss. The paper addresses this problem with a novel method based on test set modification, featuring (1) a new constrained X-identification procedure that turns a properly selected set of bits in a fully-specified test set into X-bits without fault coverage loss and (2) a new LCP (low capture power) X-filling procedure that optimally assigns 0’s and 1’s to the X-bits to reduce the switching activity of the resulting test set in capture mode. This method can be readily incorporated in any test generation flow to efficiently reduce capture power dissipation without any impact on area, timing, test set size, and fault coverage. Experimental results on benchmark circuits have shown its effectiveness. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low Capture Power / X-Identification / X-filling / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 449, DC2005-53, pp. 1-6, Nov. 2005. | |
| Paper # | DC2005-53 | |
| Date of Issue | 2005-11-25 (VLD, ICD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-171 |
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| Conference Information | |
| Committee | VLD ICD DC IPSJ-SLDM |
| Conference Date | 2005-11-30 - 2005-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design/Verification/Test of VLSI systems, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2005-11-VLD-ICD-DC-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Low Capture Power Test Generation for Scan Testing |
| Sub Title (in English) | |
| Keyword(1) | Low Capture Power |
| Keyword(2) | X-Identification |
| Keyword(3) | X-filling |
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| 1st Author's Name | Tatsuya Suzuki |
| 1st Author's Affiliation | kyushu Institute of Technology (K.I.T.) |
| 2nd Author's Name | Xiaoqing Wen |
| 2nd Author's Affiliation | kyushu Institute of Technology (K.I.T.) |
| 3rd Author's Name | Seiji Kajihara |
| 3rd Author's Affiliation | kyushu Institute of Technology (K.I.T.) |
| 4th Author's Name | Kohei Miyase |
| 4th Author's Affiliation | Japan Science and Technology Agency (JST) |
| 5th Author's Name | Yoshihiro Minamoto |
| 5th Author's Affiliation | Japan Science and Technology Agency (JST) |
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| Speaker | Author-1 |
| Date Time | 2005-12-02 09:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2005-76, ICD2005-171, DC2005-53 |
| Volume (vol) | vol.105 |
| Number (no) | no.443(VLD), no.446(ICD), no.449(DC) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2005-11-25 (VLD, ICD, DC) |
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