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| Presentation | 2005-12-01 09:30 Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) Link to ES Tech. Rep. Archives:  ICD2005-156 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable gate arrays (FPGAs). The paper shows that if the circuit structure of a configuration corresponding to an application is inphase structure, all the paths in the circuit can be robustly tested by using two configurations with test application time d+2 for each configuration where d is the maximum sequential depth of the circuit. The scheme for inphase structure is extended for acyclic structure and general structure. For cyclic sequential circuits, the original configuration is modified by configuration for testability method so that the number of test configurations for the circuit can be two. The proposed method reduces overtesting by excluding paths of outside the configured area in the FPGA. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / path delay fault / inphase structure / test configuration / configuration for testability / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 448, DC2005-38, pp. 1-6, Nov. 2005. | |
| Paper # | DC2005-38 | |
| Date of Issue | 2005-11-24 (VLD, ICD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-156 |
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| Conference Information | |
| Committee | VLD ICD DC IPSJ-SLDM |
| Conference Date | 2005-11-30 - 2005-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design/Verification/Test of VLSI systems, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2005-11-VLD-ICD-DC-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | path delay fault |
| Keyword(3) | inphase structure |
| Keyword(4) | test configuration |
| Keyword(5) | configuration for testability |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kosuke Yabuki |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name | Hideo Fujiwara |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2005-12-01 09:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2005-61, ICD2005-156, DC2005-38 |
| Volume (vol) | vol.105 |
| Number (no) | no.442(VLD), no.445(ICD), no.448(DC) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2005-11-24 (VLD, ICD, DC) |
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