| Paper Abstract and Keywords |
| Presentation |
2005-12-01 11:25
Proposal of a virus check system using FPGA
Kei Shimane (Toho Univ.), Yosuke Iijima (Univ. Of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
As regular broadband connections to the Internet are now common in homes, private users need to take measures against various security risks, such as computer viruses. We propose a new virus check method that replaces conventional virus check systems, which are implemented by software, by employing reconfigurable hardware. Our proposed method executes virus checks using an FPGA (Field Programmable Gate Array), which is a reconfigurable hardware device, with the virus check system being incorporated between the computer to be protected and the LAN. With this approach, we can realize (1) high-speed virus checks, without incurring communication bottlenecks, (2) a safer security measure, which prevents viruses from entering the protected computer, and (3) a universal security system that can be used with any type of computer (from PCs, workstations to digital home appliances). In this paper, we first outline our proposed method. Then, we describe the structure of a prototype system for principle verification, and finally we focus on key features of the proposed checking method, which involves the generation of matching logic and automatic updating of the FPGA. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Network Security / Computer Virus / Reconfigurable Hardware / FPGA / Virus Check, Hardware / Matching / 10G Ethernet / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 451, RECONF2005-63, pp. 25-30, Nov. 2005. |
| Paper # |
RECONF2005-63 |
| Date of Issue |
2005-11-24 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
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