| Paper Abstract and Keywords |
| Presentation |
2005-12-01 13:30
Architecture Overview of Reconfigurable Processor FE-GA for Digital Media Processing
Takanobu Tsunoda, Masashi Takada, Yohei Akita, Hiroshi Tanaka, Makoto Satoh, Masaki Ito (Hitachi) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
We developed a dynamically-reconfigurable processor Flexible Engine/Generic ALU array (FE-GA) targeting to digital media processing, which holds as a base structure an Operation Cell Array composed of 2-dimensionally-arrayed ALUs providing dynamically changeable functionality, and is connectable to various host CPUs. FE-GA integrates a Crossbar Network supporting internal data transfer at high level of freedom, plural banks of local memory for operation data storage, and in addition, peripheral function modules enabling effective 2-level hierarchical configuration data memory with background transfer, and autonomous sequence control, which performs as an independent subsystem. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
ALU / Dynamically Reconfigurable Processor / Crossbar Network / Hierarchical Memory / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 451, RECONF2005-65, pp. 37-41, Nov. 2005. |
| Paper # |
RECONF2005-65 |
| Date of Issue |
2005-11-24 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
RECONF |
| Conference Date |
2005-11-30 - 2005-12-02 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kitakyushu International Conference Center |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
RECONF |
| Conference Code |
2005-11-RECONF |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Architecture Overview of Reconfigurable Processor FE-GA for Digital Media Processing |
| Sub Title (in English) |
|
| Keyword(1) |
ALU |
| Keyword(2) |
Dynamically Reconfigurable Processor |
| Keyword(3) |
Crossbar Network |
| Keyword(4) |
Hierarchical Memory |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| 1st Author's Name |
Takanobu Tsunoda |
| 1st Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 2nd Author's Name |
Masashi Takada |
| 2nd Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 3rd Author's Name |
Yohei Akita |
| 3rd Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 4th Author's Name |
Hiroshi Tanaka |
| 4th Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
| 5th Author's Name |
Makoto Satoh |
| 5th Author's Affiliation |
System Development Laboratory, Hitachi, Ltd. (Hitachi) |
| 6th Author's Name |
Masaki Ito |
| 6th Author's Affiliation |
Central Research Laboratory, Hitachi, Ltd. (Hitachi) |
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| Speaker |
Author-1 |
| Date Time |
2005-12-01 13:30:00 |
| Presentation Time |
25 minutes |
| Registration for |
RECONF |
| Paper # |
RECONF2005-65 |
| Volume (vol) |
vol.105 |
| Number (no) |
no.451 |
| Page |
pp.37-41 |
| #Pages |
5 |
| Date of Issue |
2005-11-24 (RECONF) |
|