Paper Abstract and Keywords |
Presentation |
2005-11-30 13:30
[Fellow Memorial Lecture]
Layout CAD and DFM
-- Beginning and Maturity -- Takashi Mitsuhashi (Cadence Japan) Link to ES Tech. Rep. Archives: ICD2005-149 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The auther had an opportunity to be engaged in development of VLSI layout design automation, and automation of design verification, almost 30 years in Toshiba Corp. Now, the auther is involved in development of CAD for DFM (Design for Manufacturing) in Cadence Japan. This paper describes some experiences on those developments, and personal observations related to lifecyle of the technologies and experiences of the research theme selection that auther did. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
VLSI design / Design automation / Layout design / Design verification / Lifecycle of technologies / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 441, VLD2005-54, pp. 1-6, Nov. 2005. |
Paper # |
VLD2005-54 |
Date of Issue |
2005-11-23 (VLD, ICD, DC) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2005-149 |
Conference Information |
Committee |
VLD ICD DC IPSJ-SLDM |
Conference Date |
2005-11-30 - 2005-12-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu International Conference Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design/Verification/Test of VLSI systems, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2005-11-VLD-ICD-DC-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Layout CAD and DFM |
Sub Title (in English) |
Beginning and Maturity |
Keyword(1) |
VLSI design |
Keyword(2) |
Design automation |
Keyword(3) |
Layout design |
Keyword(4) |
Design verification |
Keyword(5) |
Lifecycle of technologies |
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1st Author's Name |
Takashi Mitsuhashi |
1st Author's Affiliation |
Cadence Design Systems, Japan (Cadence Japan) |
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Speaker |
Author-1 |
Date Time |
2005-11-30 13:30:00 |
Presentation Time |
50 minutes |
Registration for |
VLD |
Paper # |
VLD2005-54, ICD2005-149, DC2005-31 |
Volume (vol) |
vol.105 |
Number (no) |
no.441(VLD), no.444(ICD), no.447(DC) |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2005-11-23 (VLD, ICD, DC) |
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