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| Presentation | 2005-10-20 16:30 A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) Link to ES Tech. Rep. Archives:  ICD2005-132 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80°C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SOI-CMOS / Twin transistor / embedded memory / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 351, ICD2005-132, pp. 107-112, Oct. 2005. | |
| Paper # | ICD2005-132 | |
| Date of Issue | 2005-10-13 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-132 |
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| Conference Information | |
| Committee | SIP ICD IE IPSJ-SLDM |
| Conference Date | 2005-10-20 - 2005-10-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ichinobo, Sakunami-Spa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Processor, DSP, Image Engineering and etc. |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-10-SIP-ICD-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI |
| Sub Title (in English) | |
| Keyword(1) | SOI-CMOS |
| Keyword(2) | Twin transistor |
| Keyword(3) | embedded memory |
| Keyword(4) | |
| Keyword(5) | |
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| 1st Author's Name | Takayuki Gyohten |
| 1st Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 2nd Author's Name | Fukashi Morishita |
| 2nd Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 3rd Author's Name | Hideyuki Noda |
| 3rd Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 4th Author's Name | Mako Okamoto |
| 4th Author's Affiliation | Daioh Electric Corporation (Daioh Electric Corp.) |
| 5th Author's Name | Takashi Ipposhi |
| 5th Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 6th Author's Name | Shigeto Maegawa |
| 6th Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 7th Author's Name | Katsumi Dosaka |
| 7th Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
| 8th Author's Name | Kazutami Arimoto |
| 8th Author's Affiliation | Renesas Technology Corporation (Renesas Technology Corp.) |
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| Speaker | Author-1 |
| Date Time | 2005-10-20 16:30:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | SIP2005-113, ICD2005-132, IE2005-77 |
| Volume (vol) | vol.105 |
| Number (no) | no.349(SIP), no.351(ICD), no.353(IE) |
| Page | pp.107-112 |
| #Pages | 6 |
| Date of Issue | 2005-10-13 (SIP, ICD, IE) |
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