| Paper Abstract and Keywords |
| Presentation |
2005-09-15 13:00
On LUT cascade realizations of FIR filters using arithmetic decomposition
Tsutomu Sasao (Kyutech), Yukihiro Iguchi, Takahiro Suzuki (Meiji Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Digital filter / Distributed arithmetic / LUT cascade / Functional decomposition / inary decision diagram / FPGA / / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 287, RECONF2005-33, pp. 19-24, Sept. 2005. |
| Paper # |
RECONF2005-33 |
| Date of Issue |
2005-09-08 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
RECONF |
| Conference Date |
2005-09-15 - 2005-09-16 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Reconfigurable Systems, etc. |
| Paper Information |
| Registration To |
RECONF |
| Conference Code |
2005-09-RECONF |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
On LUT cascade realizations of FIR filters using arithmetic decomposition |
| Sub Title (in English) |
|
| Keyword(1) |
Digital filter |
| Keyword(2) |
Distributed arithmetic |
| Keyword(3) |
LUT cascade |
| Keyword(4) |
Functional decomposition |
| Keyword(5) |
inary decision diagram |
| Keyword(6) |
FPGA |
| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Tsutomu Sasao |
| 1st Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name |
Yukihiro Iguchi |
| 2nd Author's Affiliation |
Meiji University (Meiji Univ.) |
| 3rd Author's Name |
Takahiro Suzuki |
| 3rd Author's Affiliation |
Meiji University (Meiji Univ.) |
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| Speaker |
Author-3 |
| Date Time |
2005-09-15 13:00:00 |
| Presentation Time |
30 minutes |
| Registration for |
RECONF |
| Paper # |
RECONF2005-33 |
| Volume (vol) |
vol.105 |
| Number (no) |
no.287 |
| Page |
pp.19-24 |
| #Pages |
6 |
| Date of Issue |
2005-09-08 (RECONF) |