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| Presentation | 2005-09-09 14:30 [Invited Talk] On chip transmission line interconnect Kazuya Masu, Kenichi Okada, Hiroyuki Ito (Tokyo Institute of Technology) Link to ES Tech. Rep. Archives:  CPM2005-104 ICD2005-114 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recent Si CMOS performance becomes to be limited by the long global interconnect characteristics. In this paper, we discuss the performance of transmission line interconnect on Si CMOS chip. Interconnect line structure, design and evaluation of signal transmission of Tx/TR-Line/Rx circuit, and estimation and prediction of signal delay and power consumption of global interconnect in 180nm, 90nm and 45nm technology node are presented. In sub 100nm node, signal delay and power consumption of transmission line interconnect are both superior to those using the conventional RC global interconnect with repeaters. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Si CMOS / Transmission Line Interconnect / Interconnect Length Distribution / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 266, CPM2005-104, pp. 47-52, Sept. 2005. | |
| Paper # | CPM2005-104 | |
| Date of Issue | 2005-09-02 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: CPM2005-104 ICD2005-114 |
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| Conference Information | |
| Committee | ICD CPM |
| Conference Date | 2005-09-08 - 2005-09-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPM |
| Conference Code | 2005-09-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On chip transmission line interconnect |
| Sub Title (in English) | |
| Keyword(1) | Si CMOS |
| Keyword(2) | Transmission Line Interconnect |
| Keyword(3) | Interconnect Length Distribution |
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| 1st Author's Name | Kazuya Masu |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Institute of Technology) |
| 2nd Author's Name | Kenichi Okada |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Institute of Technology) |
| 3rd Author's Name | Hiroyuki Ito |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo Institute of Technology) |
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| Speaker | Author-1 |
| Date Time | 2005-09-09 14:30:00 |
| Presentation Time | 50 minutes |
| Registration for | CPM |
| Paper # | CPM2005-104, ICD2005-114 |
| Volume (vol) | vol.105 |
| Number (no) | no.266(CPM), no.268(ICD) |
| Page | pp.47-52 |
| #Pages | 6 |
| Date of Issue | 2005-09-02 (CPM, ICD) |
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