Paper Abstract and Keywords |
Presentation |
2005-09-08 09:50
Development of Design Techniques for Semiconductor-Package By using Simplified DRAM Macro Model of Power System Satoshi Nakamura, Takashi Suga (Hitachi PERL), Mitsuaki Katagiri, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose, イサ サトシ (Elpida) Link to ES Tech. Rep. Archives: CPM2005-87 ICD2005-97 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In late years, MCP(Multi Chip Package) and SiP(System in Package) which has plural semiconductor chips in one package become the mainstream in the semiconductor industry. However, by increasing of a voltage fluctuation of power supply/GND with high-speed semiconductor chips packaged in MCP/SiP, decrease of working reliability will be a big problem. By this report, for the purpose of presentation the optimum design manual to power supply/GND trace in a semiconductor package such as MCP/SiP, we make a linear macro-model of the DRAM output circuit between power supply and GND from a SPICE model. And, for a suppression of the voltage fluctuation less than arbitrary limitation at power supply pad of a DRAM, we report the derivation technique of design manual to power supply trace in a semiconductor package by using this macro-model. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MCP / SiP / power supply /GND / a voltage fluctuation / DRAM / a semiconductor package / design manual / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 265, CPM2005-87, pp. 13-18, Sept. 2005. |
Paper # |
CPM2005-87 |
Date of Issue |
2005-09-01 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: CPM2005-87 ICD2005-97 |
Conference Information |
Committee |
ICD CPM |
Conference Date |
2005-09-08 - 2005-09-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
CPM |
Conference Code |
2005-09-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Development of Design Techniques for Semiconductor-Package By using Simplified DRAM Macro Model of Power System |
Sub Title (in English) |
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Keyword(1) |
MCP / SiP |
Keyword(2) |
power supply /GND |
Keyword(3) |
a voltage fluctuation |
Keyword(4) |
DRAM |
Keyword(5) |
a semiconductor package |
Keyword(6) |
design manual |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Satoshi Nakamura |
1st Author's Affiliation |
Hitachi,Ltd.,Production Engineering Research Laboratory (Hitachi PERL) |
2nd Author's Name |
Takashi Suga |
2nd Author's Affiliation |
Hitachi,Ltd.,Production Engineering Research Laboratory (Hitachi PERL) |
3rd Author's Name |
Mitsuaki Katagiri |
3rd Author's Affiliation |
Elpida Memory,Inc. (Elpida) |
4th Author's Name |
Yoji Nishio |
4th Author's Affiliation |
Elpida Memory,Inc. (Elpida) |
5th Author's Name |
Seiji Funaba |
5th Author's Affiliation |
Elpida Memory,Inc. (Elpida) |
6th Author's Name |
Yukitoshi Hirose |
6th Author's Affiliation |
Elpida Memory,Inc. (Elpida) |
7th Author's Name |
イサ サトシ |
7th Author's Affiliation |
Elpida Memory,Inc. (Elpida) |
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Speaker |
Author-1 |
Date Time |
2005-09-08 09:50:00 |
Presentation Time |
25 minutes |
Registration for |
CPM |
Paper # |
CPM2005-87, ICD2005-97 |
Volume (vol) |
vol.105 |
Number (no) |
no.265(CPM), no.267(ICD) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2005-09-01 (CPM, ICD) |
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