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| Presentation | 2005-08-19 14:15 Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories Kazuo Otsuga, Hideaki Kurata (Hitachi, Ltd.), Kenji Kozakai, Satoshi Noda (Renesas), Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi (Hitachi, Ltd.) Link to ES Tech. Rep. Archives:  SDM2005-153 ICD2005-92 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We developed a selective-capacitance constant-charge-injection programming scheme for multilevel AG-AND flash memories. This scheme minimizes the programming time of each Vth level using optimized capacitance values. In 4-Gbit AG-AND flash memory, a local bit line capacitance is utilized for middle-level, and sum of local and global bit line capacitance is utilized for top-level. A programming throughput of 10 MB/s is achieved using this new scheme. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Flash memory / AG-AND / Multilevel Technology / Constant-Charge-Injection Programming / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 235, ICD2005-92, pp. 61-66, Aug. 2005. | |
| Paper # | ICD2005-92 | |
| Date of Issue | 2005-08-12 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: SDM2005-153 ICD2005-92 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2005-08-18 - 2005-08-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | HAKODATE KOKUSAI HOTEL |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuits, Device Technologies (High Speed, Low Voltage, Low Power), etc |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories |
| Sub Title (in English) | * |
| Keyword(1) | Flash memory |
| Keyword(2) | AG-AND |
| Keyword(3) | Multilevel Technology |
| Keyword(4) | Constant-Charge-Injection Programming |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazuo Otsuga |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
| 2nd Author's Name | Hideaki Kurata |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
| 3rd Author's Name | Kenji Kozakai |
| 3rd Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 4th Author's Name | Satoshi Noda |
| 4th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 5th Author's Name | Yoshitaka Sasago |
| 5th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
| 6th Author's Name | Tsuyoshi Arigane |
| 6th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
| 7th Author's Name | Tetsufumi Kawamura |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
| 8th Author's Name | Takashi Kobayashi |
| 8th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi, Ltd.) |
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| Speaker | Author-1 |
| Date Time | 2005-08-19 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2005-153, ICD2005-92 |
| Volume (vol) | vol.105 |
| Number (no) | no.233(SDM), no.235(ICD) |
| Page | pp.61-66 |
| #Pages | 6 |
| Date of Issue | 2005-08-12 (SDM, ICD) |
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