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| Presentation | 2005-08-19 13:50 A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) Link to ES Tech. Rep. Archives:  SDM2005-152 ICD2005-91 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operation. The write time and retention time of the twin-cell array become shorter by 50% and longer by more than 20% than those of a single cell array, enabling a 0.4-V operation. Furthermore, the cell accepts the plate-driven scheme without dummy cell, lowering the necessary word-line voltage by 0.4 V. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Twin-cell DRAM array / write time / low voltage RAM / retention time / plate-driven cell / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 235, ICD2005-91, pp. 55-60, Aug. 2005. | |
| Paper # | ICD2005-91 | |
| Date of Issue | 2005-08-12 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: SDM2005-152 ICD2005-91 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2005-08-18 - 2005-08-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | HAKODATE KOKUSAI HOTEL |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuits, Device Technologies (High Speed, Low Voltage, Low Power), etc |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell |
| Sub Title (in English) | |
| Keyword(1) | Twin-cell DRAM array |
| Keyword(2) | write time |
| Keyword(3) | low voltage RAM |
| Keyword(4) | retention time |
| Keyword(5) | plate-driven cell |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Riichiro Takemura |
| 1st Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
| 2nd Author's Name | Kiyoo Itoh |
| 2nd Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
| 3rd Author's Name | Tomonori Sekiguchi |
| 3rd Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
| 4th Author's Name | Satoru Akiyama |
| 4th Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
| 5th Author's Name | Satoru Hanzawa |
| 5th Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
| 6th Author's Name | Kazuhiko Kajigaya |
| 6th Author's Affiliation | ELPIDA Memory Inc. (ELPIDA) |
| 7th Author's Name | Takayuki Kawahara |
| 7th Author's Affiliation | Hitachi Ltd., Central Research Laboratory (Hitachi) |
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| Speaker | Author-1 |
| Date Time | 2005-08-19 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2005-152, ICD2005-91 |
| Volume (vol) | vol.105 |
| Number (no) | no.233(SDM), no.235(ICD) |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2005-08-12 (SDM, ICD) |
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