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Paper Abstract and Keywords
Presentation 2005-08-18 14:30
Delay Modeling and Static Timing Analysis for MTCMOS Circuits
Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Institute of Tech.) Link to ES Tech. Rep. Archives: SDM2005-138 ICD2005-77
Abstract (in Japanese) (See Japanese page) 
(in English) One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output parasitic capacitance, the virtual ground length, and a power switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.
Keyword (in Japanese) (See Japanese page) 
(in English) MTCMOS / Selective-MT / Circuit Delay / Static Timing Analysis / Linear Interpolation / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 234, ICD2005-77, pp. 61-66, Aug. 2005.
Paper # ICD2005-77 
Date of Issue 2005-08-11 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Conference Information
Committee ICD SDM  
Conference Date 2005-08-18 - 2005-08-19 
Place (in Japanese) (See Japanese page) 
Place (in English) HAKODATE KOKUSAI HOTEL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuits, Device Technologies (High Speed, Low Voltage, Low Power), etc 
Paper Information
Registration To ICD 
Conference Code 2005-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Delay Modeling and Static Timing Analysis for MTCMOS Circuits 
Sub Title (in English)  
Keyword(1) MTCMOS  
Keyword(2) Selective-MT  
Keyword(3) Circuit Delay  
Keyword(4) Static Timing Analysis  
Keyword(5) Linear Interpolation  
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1st Author's Name Naoaki Ohkubo  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
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Speaker
Date Time 2005-08-18 14:30:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2005-138,IEICE-ICD2005-77 
Volume (vol) IEICE-105 
Number (no) no.232(SDM), no.234(ICD) 
Page pp.61-66 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2005-08-11,IEICE-ICD-2005-08-11 


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