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Presentation 2005-07-14 15:20
An evalution of 272 gate count ODRGA_VLSI
Takenori Shiki, Minoru Watanabe, Fuminori Kobayashi (K I T) Link to ES Tech. Rep. Archives: ICD2005-50
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
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Reference Info. IEICE Tech. Rep., vol. 105, no. 184, ICD2005-50, pp. 61-65, July 2005.
Paper # ICD2005-50 
Date of Issue 2005-07-07 (ICD) 
ISSN Print edition: ISSN 0913-5685
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2005-07-14 - 2005-07-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Toyohashi Univ. of Tech. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) LSIs for analog, digital-analog mixed signal processing, sensors, and communication, etc. 
Paper Information
Registration To ICD 
Conference Code 2005-07-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An evalution of 272 gate count ODRGA_VLSI 
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1st Author's Name Takenori Shiki  
1st Author's Affiliation Kyushu Institute of Technology (K I T)
2nd Author's Name Minoru Watanabe  
2nd Author's Affiliation Kyushu Institute of Technology (K I T)
3rd Author's Name Fuminori Kobayashi  
3rd Author's Affiliation Kyushu Institute of Technology (K I T)
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Date Time 2005-07-14 15:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2005-50 
Volume (vol) vol.105 
Number (no) no.184 
Page pp.61-65 
#Pages
Date of Issue 2005-07-07 (ICD) 


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