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Paper Abstract and Keywords
Presentation 2005-06-28 13:50
Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH
Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a design of parallel multipliers based on arithmetic description language called ARITH. The multiplication algorithms in ARITH can be verified formally by formula manipulations. In this paper, we also present an application of ARITH to a multiplier module generator. The proposed system generates 352 types of parallel multipliers including those using unconventional number systems such as redundant number systems.
Keyword (in Japanese) (See Japanese page) 
(in English) arithmetic circuit / hardware description language / formal verification / / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 148, VLD2005-32, pp. 37-42, June 2005.
Paper # VLD2005-32 
Date of Issue 2005-06-21 (CAS, VLD, SIP) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee CAS SIP VLD  
Conference Date 2005-06-27 - 2005-06-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Tohoku University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal Processing, LSI, etc. 
Paper Information
Registration To VLD 
Conference Code 2005-06-CAS-SIP-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH 
Sub Title (in English)  
Keyword(1) arithmetic circuit  
Keyword(2) hardware description language  
Keyword(3) formal verification  
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1st Author's Name Yuki Watanabe  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Naofumi Homma  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Takafumi Aoki  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Tatsuo Higuchi  
4th Author's Affiliation Tohoku Institute of Technology (Tohtech)
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Speaker Author-1 
Date Time 2005-06-28 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # CAS2005-21, VLD2005-32, SIP2005-45 
Volume (vol) vol.105 
Number (no) no.146(CAS), no.148(VLD), no.150(SIP) 
Page pp.37-42 
#Pages
Date of Issue 2005-06-21 (CAS, VLD, SIP) 


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