Paper Abstract and Keywords |
Presentation |
2005-06-28 14:15
A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We focus on the reliability messages by the row-operation can be obtained from only two absolute value or three signed value. In our proposed LDPC decoder, the row-operation module outputs the minimum absolute value, second minimum value, the flag signals and the signed bits, and they are stored in memory of row-operation module. These values and signals are fed to column operation module. We implemented partially-parallel LDPC decoder based on our proposed method. Implementation result shows that memory requirement can be reduced by our implemented LDPC decoder. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
low-density parity check(LDPC) codes / min-sum algorithm / partially-parallel LDPC decoder / memory-reduction / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 148, VLD2005-33, pp. 43-48, June 2005. |
Paper # |
VLD2005-33 |
Date of Issue |
2005-06-21 (CAS, VLD, SIP) |
ISSN |
Print edition: ISSN 0913-5685 |
Download PDF |
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Conference Information |
Committee |
CAS SIP VLD |
Conference Date |
2005-06-27 - 2005-06-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Tohoku University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Signal Processing, LSI, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2005-06-CAS-SIP-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm |
Sub Title (in English) |
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Keyword(1) |
low-density parity check(LDPC) codes |
Keyword(2) |
min-sum algorithm |
Keyword(3) |
partially-parallel LDPC decoder |
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memory-reduction |
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1st Author's Name |
Tatsuyuki Ishikawa |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Kazunori Shimizu |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Takeshi Ikenaga |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Satoshi Goto |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2005-06-28 14:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
CAS2005-22, VLD2005-33, SIP2005-46 |
Volume (vol) |
vol.105 |
Number (no) |
no.146(CAS), no.148(VLD), no.150(SIP) |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2005-06-21 (CAS, VLD, SIP) |