| Paper Abstract and Keywords |
| Presentation |
2005-06-28 14:25
Design and Evaluation of a Bit-Parallel Magnitude-Comparison CAM Based on TMR Logic
Kohei Shoji, Takahiro Hanyu (Tohoku Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
The paper presents a new circuit style called ``TMR logic" combining TMR(tunneling magnetoresistive) devices with connected MOS pass-transistor network, which results merging storage function into logic circuit plane with a small area. Since the TMR device can be regarded as a variable resistor with non-volatile storage capability, the logic function can be realized by series and parallel connection of the TMR devices and transistors. As a typical example, a content-addressable memory(CAM) where magnitude-compare in a bit-parallel fashion simply implemented based on TMR logic and its performance improvement is also demonstrated. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
MRAM / TMR / MR ratio / nonvolatile logic / wired logic / content-addressable memory / / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 150, SIP2005-48, pp. 55-59, June 2005. |
| Paper # |
SIP2005-48 |
| Date of Issue |
2005-06-21 (CAS, VLD, SIP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
CAS SIP VLD |
| Conference Date |
2005-06-27 - 2005-06-28 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Tohoku University |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Signal Processing, LSI, etc. |
| Paper Information |
| Registration To |
SIP |
| Conference Code |
2005-06-CAS-SIP-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Design and Evaluation of a Bit-Parallel Magnitude-Comparison CAM Based on TMR Logic |
| Sub Title (in English) |
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| Keyword(1) |
MRAM |
| Keyword(2) |
TMR |
| Keyword(3) |
MR ratio |
| Keyword(4) |
nonvolatile logic |
| Keyword(5) |
wired logic |
| Keyword(6) |
content-addressable memory |
| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Kohei Shoji |
| 1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
| 2nd Author's Name |
Takahiro Hanyu |
| 2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2005-06-28 14:25:00 |
| Presentation Time |
25 minutes |
| Registration for |
SIP |
| Paper # |
CAS2005-24, VLD2005-35, SIP2005-48 |
| Volume (vol) |
vol.105 |
| Number (no) |
no.146(CAS), no.148(VLD), no.150(SIP) |
| Page |
pp.55-59 |
| #Pages |
5 |
| Date of Issue |
2005-06-21 (CAS, VLD, SIP) |