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Paper Abstract and Keywords
Presentation 2005-05-19 14:50
A study on high speed arithmetic of FDTD method using FPGA implementing
Hidetoshi Suzuki, Yuta Takagi, Ryo Yamaguchi, Shinji Uebayashi (NTTDoCoMo Inc.)
Abstract (in Japanese) (See Japanese page) 
(in English) We have examined the FPGA (Field Programmable Gate Array) implementation of the FDTD algorithm to accelerate the electromagnetic field simulation. So far, we evaluated the calculation error of the fix-point arithmetic for the FDTD method and we showed that the error of less than 0.01 is realized when the bit length is more than 28bits. In this paper, the examination to shorten the time of FDTD calculation by FPGA used 32bit-operation machine is showed. At first, the architecture of the FPGA hardware is described. Next, the analysis of the processing time in the case of untouched FPGA implementation is described and it is showed that the access time to an external memory for FPGA becomes dominant of the processing time because of the shortening of the calculation time by the pipeline processing. We focus the reduction of the number of reading data from DDR memory and examine the improvement techniques. As a result, we showed that the techniques achieves the about 1/22 calculation time compared with the time by one PC using the commercial software, and the error of less than 0.01 compared with the floating point arithmetic.
Keyword (in Japanese) (See Japanese page) 
(in English) FDTD / FPGA / FPGA implementation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 59, AP2005-18, pp. 51-56, May 2005.
Paper # AP2005-18 
Date of Issue 2005-05-12 (AP) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee AP SAT  
Conference Date 2005-05-19 - 2005-05-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Tottori Univ. of Environmental Studies 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Antenna and Propagation in Satellite Communications and Satellite Communication in General 
Paper Information
Registration To AP 
Conference Code 2005-05-AP-SAT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study on high speed arithmetic of FDTD method using FPGA implementing 
Sub Title (in English)  
Keyword(1) FDTD  
Keyword(2) FPGA  
Keyword(3) FPGA implementation  
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1st Author's Name Hidetoshi Suzuki  
1st Author's Affiliation NTTDoCoMo Inc. (NTTDoCoMo Inc.)
2nd Author's Name Yuta Takagi  
2nd Author's Affiliation NTTDoCoMo Inc. (NTTDoCoMo Inc.)
3rd Author's Name Ryo Yamaguchi  
3rd Author's Affiliation NTTDoCoMo Inc. (NTTDoCoMo Inc.)
4th Author's Name Shinji Uebayashi  
4th Author's Affiliation NTTDoCoMo Inc. (NTTDoCoMo Inc.)
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Speaker Author-1 
Date Time 2005-05-19 14:50:00 
Presentation Time 25 minutes 
Registration for AP 
Paper # AP2005-18 
Volume (vol) vol.105 
Number (no) no.59 
Page pp.51-56 
#Pages
Date of Issue 2005-05-12 (AP) 


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