Paper Abstract and Keywords |
Presentation |
2005-04-15 13:00
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme -- Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL) Link to ES Tech. Rep. Archives: ICD2005-16 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents high speed and low-power circuit techniques for small size SRAMs (e.g., on-chip cache memories). Read-out time is shortened by using the I/O-separated memory cell including a tri-state driver. The use of CMOS transfer gates with a dual wordline guarantees the sure writing operation under the single bitline scheme. Word divers are kept at a high impedance state after selecting a wordline, resulting in a shorter operation time to unselect the wordline. As to a low-power technique, the authors propose to use an NRZ-type writing-enable signal. In the design of memory array, a hierarchical bitline scheme is adopted; each local bitline is installed dedicated I/O circuitry to write or read data. Owing to the small parasitic capacitance due to only sixteen cells per local bitline, it is possible to read without pulling up or precharging the local bitlines. A 1K-words×36-bits SRAM test chip fabricated with a 0.25-μm CMOS/SIMOX process has demonstrated a 1.5-ns address access time and 40 mW @2V/500MHz for the row-bar test pattern. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS / SRAM / Dual Wordline / Hierarchical Bitline Scheme / SIMOX / Fully Depleted MOSFET / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 2, ICD2005-16, pp. 19-24, April 2005. |
Paper # |
ICD2005-16 |
Date of Issue |
2005-04-08 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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Link to ES Tech. Rep. Archives: ICD2005-16 |
Conference Information |
Committee |
ICD |
Conference Date |
2005-04-14 - 2005-04-15 |
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(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2005-04-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell |
Sub Title (in English) |
High Speed and Low-Power Operation by Using Dual-Wordline Scheme |
Keyword(1) |
CMOS |
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SRAM |
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Dual Wordline |
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Hierarchical Bitline Scheme |
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SIMOX |
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Fully Depleted MOSFET |
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1st Author's Name |
Nobutaro Shibata |
1st Author's Affiliation |
NTT (NTT) |
2nd Author's Name |
Takako Ishihara |
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NTT (NTT) |
3rd Author's Name |
Shigehiro Kurita |
3rd Author's Affiliation |
NTT Electronics (NEL) |
4th Author's Name |
Hideomi Okiyama |
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NTT Electronics (NEL) |
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Speaker |
Author-1 |
Date Time |
2005-04-15 13:00:00 |
Presentation Time |
30 minutes |
Registration for |
ICD |
Paper # |
ICD2005-16 |
Volume (vol) |
vol.105 |
Number (no) |
no.2 |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2005-04-08 (ICD) |
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