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| Presentation | 2005-04-14 16:15 4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS) Link to ES Tech. Rep. Archives:  ICD2005-11 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline technology, the bit-line pitch is reduced to 2 F, resulting in a 126 mm2 chip size and a 0.0162um2/bit cell size. To achieve 2-bits/cell, we have to precisely control the large resistance of the inversion-layer bit-line. In reading operations, two compensation methods, the address compensation and temperature compensation methods, were applied. In programming operations, charge-sharing scheme suppresses the difference in programming speeds along the string and self-boosting scheme reduces the time overhead of pre-charging bitlines. With these two schemes, a high programming throughput of 10 MB/s is achieved, even in multilevel flash memory. We have also provided a cache-read function to achieve a high access throughput of 22 MB/s. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | multilevel / flash memory / AG-AND-type / inversion-layer bit-line / self-boosting / charge-sharing / temperature conmensation / address compensation | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 1, ICD2005-11, pp. 53-58, April 2005. | |
| Paper # | ICD2005-11 | |
| Date of Issue | 2005-04-07 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-11 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2005-04-14 - 2005-04-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput |
| Sub Title (in English) | |
| Keyword(1) | multilevel |
| Keyword(2) | flash memory |
| Keyword(3) | AG-AND-type |
| Keyword(4) | inversion-layer bit-line |
| Keyword(5) | self-boosting |
| Keyword(6) | charge-sharing |
| Keyword(7) | temperature conmensation |
| Keyword(8) | address compensation |
| 1st Author's Name | Hideaki Kurata |
| 1st Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 2nd Author's Name | Yoshitaka Sasago |
| 2nd Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 3rd Author's Name | Kazuo Otsuga |
| 3rd Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 4th Author's Name | Tsuyoshi Arigane |
| 4th Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 5th Author's Name | Tetsufumi Kawamura |
| 5th Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 6th Author's Name | Takashi Kobayashi |
| 6th Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 7th Author's Name | Hitoshi Kume |
| 7th Author's Affiliation | Hitachi Ltd. (Hitachi) |
| 8th Author's Name | Kazuki Homma |
| 8th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 9th Author's Name | Kenji Kozakai |
| 9th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 10th Author's Name | Satoshi Noda |
| 10th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 11th Author's Name | Teruhiko Ito |
| 11th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 12th Author's Name | Masahiro Shimizu |
| 12th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 13th Author's Name | Yoshihiro Ikeda |
| 13th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 14th Author's Name | Osamu Tsuchiya |
| 14th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 15th Author's Name | Kazunori Furusawa |
| 15th Author's Affiliation | Renesas Technology Corp. (RENESAS) |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2005-04-14 16:15:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2005-11 |
| Volume (vol) | vol.105 |
| Number (no) | no.1 |
| Page | pp.53-58 |
| #Pages | 6 |
| Date of Issue | 2005-04-07 (ICD) |
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