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Paper Abstract and Keywords
Presentation 2005-04-14 09:00
A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications
Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) Link to ES Tech. Rep. Archives: ICD2005-1
Abstract (in Japanese) (See Japanese page) 
(in English) A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors used to achieve both low-VDD and high-speed operation. A 64kb SRAM macro is fabricated in 90nm CMOS technology. Both a minimum VDD of 440mV and a 20ns access time with a 0.5V supply are obtained.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / Static noise margin / Write margin / / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 1, ICD2005-1, pp. 1-6, April 2005.
Paper # ICD2005-1 
Date of Issue 2005-04-07 (ICD) 
ISSN Print edition: ISSN 0913-5685
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2005-04-14 - 2005-04-15 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2005-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) Static noise margin  
Keyword(3) Write margin  
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1st Author's Name Koichi Takeda  
1st Author's Affiliation NEC (NEC)
2nd Author's Name Yasuhiko Hagihara  
2nd Author's Affiliation NEC (NEC)
3rd Author's Name Yoshiharu Aimoto  
3rd Author's Affiliation NEC Electronics (NECEL)
4th Author's Name Masahiro Nomura  
4th Author's Affiliation NEC (NEC)
5th Author's Name Yoetsu Nakazawa  
5th Author's Affiliation NEC (NEC)
6th Author's Name Toshio Ishii  
6th Author's Affiliation NEC Electronics (NECEL)
7th Author's Name Hiroyuki Kobatake  
7th Author's Affiliation NEC Electronics (NECEL)
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Speaker Author-1 
Date Time 2005-04-14 09:00:00 
Presentation Time 30 minutes 
Registration for ICD 
Paper # ICD2005-1 
Volume (vol) vol.105 
Number (no) no.1 
Page pp.1-6 
#Pages
Date of Issue 2005-04-07 (ICD) 


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