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| Presentation | 2005-01-28 16:45 Development of Multiple Fault Diagnosis Based on Path-Tracing for Logic LSIs Yukihisa Funatsu, Hiroshi Sumitomo, Kazuki Shigeta, Toshio Ishiyama (NECEL) Link to ES Tech. Rep. Archives:  CPM2004-174 ICD2004-219 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | For recent highly integrated and shrunk LSIs, CAD-based fault diagnosis technology which supports physical failure analysis has become more impotant,. Our group has proposed and developed fault diagnosis technique of several types of a single fault (stuck-at, open, and bridging fault). In this paper, we report a fault diagnosis method for multiple faults. The method classifies fault effect propagation paths in a circuit and its results. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | fault diagnosis / logic circuit / multi fault / path trace / sequential circuit / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 104, no. 629, ICD2004-219, pp. 71-76, Jan. 2005. | |
| Paper # | ICD2004-219 | |
| Date of Issue | 2005-01-21 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: CPM2004-174 ICD2004-219 |
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| Conference Information | |
| Committee | ICD CPM |
| Conference Date | 2005-01-27 - 2005-01-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-01-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Multiple Fault Diagnosis Based on Path-Tracing for Logic LSIs |
| Sub Title (in English) | |
| Keyword(1) | fault diagnosis |
| Keyword(2) | logic circuit |
| Keyword(3) | multi fault |
| Keyword(4) | path trace |
| Keyword(5) | sequential circuit |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yukihisa Funatsu |
| 1st Author's Affiliation | NEC Electronics (NECEL) |
| 2nd Author's Name | Hiroshi Sumitomo |
| 2nd Author's Affiliation | NEC Electronics (NECEL) |
| 3rd Author's Name | Kazuki Shigeta |
| 3rd Author's Affiliation | NEC Electronics (NECEL) |
| 4th Author's Name | Toshio Ishiyama |
| 4th Author's Affiliation | NEC Electronics (NECEL) |
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| Speaker | Author-1 |
| Date Time | 2005-01-28 16:45:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | CPM2004-174, ICD2004-219 |
| Volume (vol) | vol.104 |
| Number (no) | no.627(CPM), no.629(ICD) |
| Page | pp.71-76 |
| #Pages | 6 |
| Date of Issue | 2005-01-21 (CPM, ICD) |
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