| Paper Abstract and Keywords |
| Presentation |
2005-01-26 13:40
Design and Development of Microprocessors on a Hardware/Software Colearning System
Koichiro Nakamura, Hoang Anh Tuan, Shigeru Oyanagi, Katsuhiro Yamazaki (Ritsumeikan University) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
The hardware/software co-learning system helps user to learn both hardware and software such as assembly programming, processor design and verification using FPGA boards by understanding processor architecture. This paper describes how to learn both hardware and software on this system. We have developed single cycle, multi cycle, pipeline and superscalar microprocessors based on a basic instruction set for this system. In addition, a single cycle microprocessor for another instruction set is described. At last we discuss about a support system for developing a processor which aims to efficiently debug both hardware and software. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Hardware/Software Co-learning System / Microprocessor / Processor Architecture / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 104, no. 592, CPSY2004-82, pp. 37-42, Jan. 2005. |
| Paper # |
CPSY2004-82 |
| Date of Issue |
2005-01-19 (VLD, CPSY) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
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| Conference Information |
| Committee |
CPSY VLD IPSJ-SLDM |
| Conference Date |
2005-01-25 - 2005-01-26 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
FPGA and its Application, etc |
| Paper Information |
| Registration To |
CPSY |
| Conference Code |
2005-01-CPSY-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Design and Development of Microprocessors on a Hardware/Software Colearning System |
| Sub Title (in English) |
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| Keyword(1) |
Hardware/Software Co-learning System |
| Keyword(2) |
Microprocessor |
| Keyword(3) |
Processor Architecture |
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| 1st Author's Name |
Koichiro Nakamura |
| 1st Author's Affiliation |
Graduate School of Ritsumeikan University (Ritsumeikan University) |
| 2nd Author's Name |
Hoang Anh Tuan |
| 2nd Author's Affiliation |
Graduate School of Ritsumeikan University (Ritsumeikan University) |
| 3rd Author's Name |
Shigeru Oyanagi |
| 3rd Author's Affiliation |
Graduate School of Ritsumeikan University (Ritsumeikan University) |
| 4th Author's Name |
Katsuhiro Yamazaki |
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Graduate School of Ritsumeikan University (Ritsumeikan University) |
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| Speaker |
Author-1 |
| Date Time |
2005-01-26 13:40:00 |
| Presentation Time |
30 minutes |
| Registration for |
CPSY |
| Paper # |
VLD2004-116, CPSY2004-82 |
| Volume (vol) |
vol.104 |
| Number (no) |
no.590(VLD), no.592(CPSY) |
| Page |
pp.37-42 |
| #Pages |
6 |
| Date of Issue |
2005-01-19 (VLD, CPSY) |