Paper Abstract and Keywords |
Presentation |
2005-01-25 10:00
Reconfigurable 1-bit processor array with reduced wiring area Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement and shortening production cycle, production cost is increasing. One of the way to solve this problem is to use of reconfigurable hardwares. Although reconfigurable hardwares seemed to be useful, they have some disadvantages. As a result, a system using software or ASIC costs lower than reconfigurable hardware in many cases. In this paper we propose an efficient architecture of reconfigurable hardware with low cost. The proposed architecture has the following features; It has high routability but wiring area is reduced, and number of processor elements can be increase easily. We mapped DCT circuit to proposed architecture and run. We also show some experimental results. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
reconfigurable computing / coarse-grain architecture / bit-serial data path / wiring resource / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 104, pp. 7-12, Jan. 2005. |
Paper # |
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Date of Issue |
2005-01-18 (VLD, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 |
Download PDF |
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Conference Information |
Committee |
CPSY VLD IPSJ-SLDM |
Conference Date |
2005-01-25 - 2005-01-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA and its Application, etc |
Paper Information |
Registration To |
IPSJ-SLDM |
Conference Code |
2005-01-CPSY-VLD-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Reconfigurable 1-bit processor array with reduced wiring area |
Sub Title (in English) |
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Keyword(1) |
reconfigurable computing |
Keyword(2) |
coarse-grain architecture |
Keyword(3) |
bit-serial data path |
Keyword(4) |
wiring resource |
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1st Author's Name |
Nobuo Nakai |
1st Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
2nd Author's Name |
Masaki Nakanishi |
2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
3rd Author's Name |
Shigeru Yamashita |
3rd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
4th Author's Name |
Katsumasa Watanabe |
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Nara Institute of Science and Technology (NAIST) |
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Speaker |
Author-1 |
Date Time |
2005-01-25 10:00:00 |
Presentation Time |
30 minutes |
Registration for |
IPSJ-SLDM |
Paper # |
VLD2004-98, CPSY2004-64 |
Volume (vol) |
vol.104 |
Number (no) |
no.589(VLD), no.591(CPSY) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2005-01-18 (VLD, CPSY) |