IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2004-11-04 11:20
Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coeficient Set
Keisuke Sato, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) For synthesis of linear transformation circuits, it is generally used that the coefficient matrix is partitioned
into multiple constant multiplication(MCM) circuits and their outputs are added. The linear transform
circuit can also be represented as an expansion of a single input and coefficient of the MCM circuit into multiple
inputs and coefficients. With this representation, the linear transform circuit can be synthesized without the final
additions. However, this synthesis method have a problem that arithmetic cost much depends on the synthesis order
of coefficient sets. In this research, we propose a synthesis method of linear transformation circuits that can reduce
arithmetic cost using a combinatorial optimization algorithm.
Keyword (in Japanese) (See Japanese page) 
(in English) Linear Transformation Circuits / Optimization Algorithm / Multiple Constant Multiplicatoin / Arithmetic Cost / / / /  
Reference Info. IEICE Tech. Rep., vol. 104, no. 402, CAS2004-46, pp. 25-28, Nov. 2004.
Paper # CAS2004-46 
Date of Issue 2004-10-28 (CAS, CST) 
ISSN Print edition: ISSN 0913-5685
Download PDF

Conference Information
Committee MSS CAS  
Conference Date 2004-11-04 - 2004-11-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Aichi Pref. Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Graph theory, Petri net, Neural network, etc. 
Paper Information
Registration To CAS 
Conference Code 2004-11-CST-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coeficient Set 
Sub Title (in English)  
Keyword(1) Linear Transformation Circuits  
Keyword(2) Optimization Algorithm  
Keyword(3) Multiple Constant Multiplicatoin  
Keyword(4) Arithmetic Cost  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Keisuke Sato  
1st Author's Affiliation Kanagawa University (Kanagawa Univ.)
2nd Author's Name Takao Sasaki  
2nd Author's Affiliation Kanagawa University (Kanagawa Univ.)
3rd Author's Name Hisamichi Toyoshima  
3rd Author's Affiliation Kanagawa University (Kanagawa Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2004-11-04 11:20:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2004-46, CST2004-25 
Volume (vol) vol.104 
Number (no) no.402(CAS), no.404(CST) 
Page pp.25-28 
#Pages
Date of Issue 2004-10-28 (CAS, CST) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan