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Paper Abstract and Keywords
Presentation 2004-10-22 15:50
Bus architecture optimization method for IP-based design
Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) Link to ES Tech. Rep. Archives: ICD2004-133
Abstract (in Japanese) (See Japanese page) 
(in English) In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly affects the performance of the target system. This paper proposes a bus architecture optimization method using fast performance estimation. The optimization problem of bus architecture that is parameterized by bus topology, bus data transfer rate, bus bit width, and the number of buffers, is formalized and its exploration method is proposed. Proposed method explores all possible bus parameter sets estimating the performance and hardware area with profiling information. Experimental results show that proposed method can determine the optimal bus architecture and its time is drastically reduced compared to the conventional method.
Keyword (in Japanese) (See Japanese page) 
(in English) IP-based design / bus architecture / performance estimation / branch-and-bound method / / / /  
Reference Info. IEICE Tech. Rep., vol. 104, no. 364(SIP), 366(ICD), 368(IE), SIP2004-101, ICD2004-133, IE2004-77, pp. 73-78, Oct. 2004.
Paper #  
Date of Issue 2004-10-15 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2004-133

Conference Information
Conference Date 2004-10-21 - 2004-10-22 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To IPSJ-SLDM 
Conference Code 2004-10-IE-SIP-ICD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Bus architecture optimization method for IP-based design 
Sub Title (in English)  
Keyword(1) IP-based design  
Keyword(2) bus architecture  
Keyword(3) performance estimation  
Keyword(4) branch-and-bound method  
1st Author's Name Kyoko Ueda  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Keishi Sakanushi  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Noboru Yoneoka  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Yoshinori Takeuchi  
4th Author's Affiliation Osaka University (Osaka Univ.)
5th Author's Name Masaharu Imai  
5th Author's Affiliation Osaka University (Osaka Univ.)
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Date Time 2004-10-22 15:50:00 
Presentation Time 25 
Registration for IPSJ-SLDM 
Paper # IEICE-SIP2004-101,IEICE-ICD2004-133,IEICE-IE2004-77 
Volume (vol) IEICE-104 
Number (no) no.364(SIP), no.366(ICD), no.368(IE) 
Page pp.73-78 
#Pages IEICE-6 
Date of Issue IEICE-SIP-2004-10-15,IEICE-ICD-2004-10-15,IEICE-IE-2004-10-15 

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