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Paper Abstract and Keywords
Presentation 2004-10-22 11:15
Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure (Hitachi), Seiji Takeuchi (Renesas), Yuichi Abe, Hiromichi Yamada (Hitachi), Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka (Renesas), Takanori Shimura (Hitachi) Link to ES Tech. Rep. Archives: ICD2004-125
Abstract (in Japanese) (See Japanese page) 
(in English) A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing. The core achieved 360MIPS and 400MFLOPS at 200MHz measured using Dhrystone 1.1. For smaller code size, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is an average of 1.8 times faster than the previous designed core. The superscalar structure and the register bank are used to save CPU registers to the resister bank in parallel when executing interrupt processing. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
Keyword (in Japanese) (See Japanese page) 
(in English) Microcontroller / RISC / Smaller code size / Low-latency / Interrupt response time / / /  
Reference Info. IEICE Tech. Rep., vol. 104, no. 366, ICD2004-125, pp. 25-30, Oct. 2004.
Paper # ICD2004-125 
Date of Issue 2004-10-15 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee IE SIP ICD IPSJ-SLDM  
Conference Date 2004-10-21 - 2004-10-22 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2004-10-IE-SIP-ICD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications 
Sub Title (in English)  
Keyword(1) Microcontroller  
Keyword(2) RISC  
Keyword(3) Smaller code size  
Keyword(4) Low-latency  
Keyword(5) Interrupt response time  
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1st Author's Name Yasuo Sugure  
1st Author's Affiliation Hitachi Ltd. (Hitachi)
2nd Author's Name Seiji Takeuchi  
2nd Author's Affiliation Renesas Technology Corp. (Renesas)
3rd Author's Name Yuichi Abe  
3rd Author's Affiliation Hitachi Ltd. (Hitachi)
4th Author's Name Hiromichi Yamada  
4th Author's Affiliation Hitachi Ltd. (Hitachi)
5th Author's Name Kazuya Hirayanagi  
5th Author's Affiliation Renesas Technology Corp. (Renesas)
6th Author's Name Akihiko Tomita  
6th Author's Affiliation Renesas Technology Corp. (Renesas)
7th Author's Name Kesami Hagiwara  
7th Author's Affiliation Renesas Technology Corp. (Renesas)
8th Author's Name Takeshi Kataoka  
8th Author's Affiliation Renesas Technology Corp. (Renesas)
9th Author's Name Takanori Shimura  
9th Author's Affiliation Hitachi Ltd. (Hitachi)
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Speaker
Date Time 2004-10-22 11:15:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SIP2004-93,IEICE-ICD2004-125,IEICE-IE2004-69 
Volume (vol) IEICE-104 
Number (no) no.364(SIP), no.366(ICD), no.368(IE) 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-SIP-2004-10-15,IEICE-ICD-2004-10-15,IEICE-IE-2004-10-15 


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