IEICE Technical Report

Online edition: ISSN 2432-6380

Volume 120, Number 122

Dependable Computing

Workshop Date : 2020-07-30 - 2020-07-31 / Issue Date : 2020-07-23

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Table of contents

DC2020-1
Instruction Prefetcher focusing on properties of Prefetch Distance
Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo)
pp. 1 - 8

DC2020-2
Distributed Runtime Environment with Julia Language
Hidemoto Nakada (AIST)
pp. 9 - 14

DC2020-3
(See Japanese page.)
pp. 15 - 21

DC2020-4
Automated Fixed-Point Bit-Length Optimization for OS-ELM
Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
pp. 23 - 28

DC2020-5
Preliminary examination of normally-off power management for local 5G base station
Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura (UTokyo)
pp. 29 - 35

DC2020-6
Proposal for an IP-based Design Environment for CGRA Applications
Ayaka Ohwada, Takuya Kojima, Hideharu Amano (Keio Univ.)
pp. 37 - 42

DC2020-7

Takuya Kojima, Ayaka Ohwada, Hideharu Amano (Keio Univ.)
pp. 43 - 48

DC2020-8
A Case for Acceleration of 2D Graph-Based SLAM using FPGA
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 49 - 54

DC2020-9
The next generation FiC with M-KUBOS board
Hideharu Amano, Kazuei Hironaka, Kensuke Iizuka (Keio Univ.)
pp. 55 - 60

DC2020-10
Task Offloading of a Distributed and Cooperative Cache Server using FPGA
Teppei Yamagishi (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
pp. 61 - 66

DC2020-11
A study of an FPGA-based cluster computing with high-speed serial links
Fan Ruochong, Ao Yun, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba)
pp. 67 - 73

DC2020-12
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)
pp. 75 - 80

DC2020-13
A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount
Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)
pp. 81 - 86

DC2020-14

Daichi Minamide, Tatsuhiro Tsuchiya (Osaka Univ.)
pp. 87 - 92

DC2020-15
An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 93 - 98

DC2020-16
A Study on Error Correction Coding For Matrix Multiplications Based On Product Codes
Yuki Katsu, Haruhiko Kaneko (Titech)
pp. 99 - 104

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan