(1) K. Itoh, “Trends in Megabit DRAM Circuit Design,”
IEEE J. Solid-State Circuits, Vol. 25, No. 3, pp. 778-789, Jun. 1990.
(2) K. Itoh, K. Sasaki and Y. Nakagome,
“Trends in Low-Power RAM Circuit Technologies,”
Proc. IEEE, Vol. 83, No. 4, pp. 524-543, Apr. 1995.
(3) Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh,
“Reviews and Future Prospects of Low-Voltage RAM Circuits,”
IBM J. R&D, Vol.47, No.5/6, pp.525-552, Sep./Nov. 2003.