Modern general-purpose microprocessors, the central processing units (CPUs) of computers, incorporate various mechanisms to speed up the execution of instruction sequences. The performance of microprocessors is determined by a complex interference between the characteristics of the program instruction sequence to be executed and the effects of these mechanisms. Hence, it is not easy to quantitatively discuss the overall behavior and predict performance. Therefore, modeling the behavior of microprocessors so that it can be explained mathematically is a very important attempt to provide guidelines for the program optimization of applications to be executed and for the design of future microprocessor architectures.

This paper focuses on the characteristics of instruction cache misses as a performance metric in a microprocessor with a decoupled front-end, in which a fetch target queue separates the branch predictor and instruction cache access. While the number of instruction cache misses is generally considered to be highly correlated with performance degradation, this paper points out that, for a processor with a decoupled front-end, the number of instruction cache misses cannot always explain the performance of the processor. Therefore, this paper proposes a new metric called "Miss Region," which is the region of the executed instruction sequence between two branch prediction misses and includes instruction cache misses. This paper also constructs a performance model that predicts performance based on this metric. The evaluation results show that the authors have succeeded in predicting the performance of a processor with a modern configuration with an average error of 1.0% and a maximum error of 4.1%.

This paper shows that (1) the performance model is clarified using a relatively simple metric and mathematical methods, (2) the metric is relatively simple yet highly accurate, and (3) the front-end modeling in this paper has enabled us to develop a new model for the entire microprocessor, including the back-end. For these reasons, this paper is highly commended as worthy of the IEICE Best Paper award.