In response to the exponential increase in wireless data rates in recent years, the 5th generation mobile communication system (5G) requires high data rate communications, using phase-array transceivers at millimeter waves such as 28 GHz. Phased array is a method of achieving long-distance communications by giving directivity to signals with multiple transceiver circuits and antennas in multiple parallel systems. Expectations are also growing for dual-polarization Multi-Input Multi-Output (MIMO) phased-array transceivers, which can transmit and receive signals independently using dual polarizations, enabling data rates twice as high as conventional rates.

In phased-array transceivers, the directivity can be controlled by high-precision phase and amplitude adjustment within each transceiver circuit. On the other hand, process and power supply mismatches among transceiver circuits can cause directivity control deviations and increased sidelobes. Therefore, a mismatch detection circuit is essential for the implementation of phased array transceivers to calibrate them as needed.

In this paper, a high-accuracy phase and amplitude detection circuit is proposed for mismatch calibration of a 28-GHz-band dual-polarization MIMO phased array transceiver, using a phase-to-digital converter (PDC) and an analog-to-digital converter (ADC). By digitally detecting the phase and amplitude of the input signal independently using the PDC and ADC, signal detection with a detection error of 0.17 degrees and a very small error of 0.12 dB can be achieved. This is a much higher detection accuracy than that of conventional methods. In addition, this detection circuit can be assumed that while one of the two polarizations is being detected, the other can be reused as an LO input to the detection circuit. This enables highly efficient implementation in transceivers. The LO signal is input into a highly linear mixer to reduce the 28 GHz input frequency to 140 kHz for digital input. Furthermore, by reusing part of the LO signal and inputting it into a frequency division multistage circuit, a 600 MHz clock signal is internally generated for digital circuit operation. Thus, high-accuracy and efficient phase and amplitude detection can be achieved.

This paper will be highly evaluated as a paper worthy of the IEICE Best Paper Award, because of its significant contribution to the realization of high-speed MIMO communications for 5G and its indispensability in improving the accuracy of millimeter-wave phased-array transceivers.