Best Paper Award

  With the rapid development of Information and Communication Technology (ICT), energy-efficient LSI circuits integrated into ICT devices are highly required from the viewpoint of extending the lifetime of battery-powered devices as well as achieving a low-carbon society. Downscaling the supply voltage to near the MOSFETs' threshold voltage is an effective technique for improving the energy-efficiency of LSI circuits. However, the voltage scaling technique makes stable operation of the LSI circuits difficult since their reliability is significantly degraded in the aggressively scaled voltage region. CMOS latches, which are commonly used as storage elements, are dominant components that determine the minimum operating voltage of digital LSI circuits. It is thus essential to perform a stability analysis of these latches and to improve their stability to lower the minimum operating voltage.
  This paper proposes a modeling method to accurately predict yields of latches operating in the weak inversion region. Based on the current-voltage characteristics of MOSFETs, this paper analytically derives conditions for the stable operation of latches. Conventionally, designers have to perform the time-consuming brute force Monte Carlo simulation in order to obtain the yield of high-yield latches. The proposed method in this paper, on the other hand, makes it possible to obtain the yield by just calculating the simple equation determined by the proposed condition. The proposed modeling method is verified through not only transistor-level circuit simulation but also silicon measurement. Based on the proposed modeling method, this paper then discusses a transistor sizing method to improve the latch yield.
  The modeling method proposed in this paper is a key technique enabling to design ultra-low-voltage LSI circuits and to thus improve their energy-efficiency. Due to the major contributions described above, this paper deserves the IEICE Best Paper Award.