Best Paper Award 2014

Best Paper Award

A Novel Detection and Recovery Techniques for Physical Defect in FPGA-IP Cores

Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga,
Toshinori Sueyoshi

[Trans. Inf. & Syst. (JPN Edition), Vol. J96-D No.12, Dec. 2013]

Motoki Amagasaki	Yuki Nishitani	Kazuki Inoue	Masahiro Iida
Morihiro Kuga	Toshinori Sueyoshi

  Fault-tolerant systems play an important role in today's advanced information-intensive society. Current fault-tolerant systems require not only high tolerance to faults, but also low overhead, e.g., small area, low power, and short delay. In this paper, the authors propose a fault-tolerant system based on FPGA (field-programmable gate array) - IP (intellectual property) cores. An FPGA is a flexible device -- it can be arbitrarily configured in the field. The proposed system utilizes this flexibility of FPGAs for fault tolerance. When detecting a failure, this system can detach the faulty parts responsible for this failure and reconfigure itself with the remaining fault-free parts, and thus recover from the failure. Note that, unlike N-Modular Redundancy, this system does not require any redundancy, so that it can keep the overhead low.
  There are two important issues for this kind of fault-tolerant systems fault detection (or identification) and reconfiguration. The authors’ novel fault detection method, which is an extension of their previous production testing method, can identify the faulty part completely with a short testing time. Their reconfiguration method, on the other hand, can efficiently recovery from failure. This is because it employs a CAD (computer-aided design) tool, which has high placing and routing ability. Experimental results show that the proposed system can completely identify given faults and avoid them with almost no performance degradation; it can be applied to practical systems requiring high reliability.
  Since FPGA-IP cores are expected to be frequently and widely utilized in the future, fault-tolerant systems with FPGA-IP cores will be a mainstream approach to obtaining high-reliability systems. This paper, in which such a fault-tolerant system is clearly designated, is worthy of the IEICE Best Paper Award.