Best Paper Award 2014

Best Paper Award

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata

[Trans. Electron., Vol. E97-C No.6, Jun. 2014]

Satoshi Takaya

Hiroaki Ikeda

Makoto Nagata

  Low power electronics will continue to evolve with three dimensional (3D) integration technology. Through silicon vias (TSVs), a key enabler of vertical digital data transmission between stacked dice, reduce the length of signal routing as well as the associated parasitic capacitance. This will lead to significant improvements in the data bandwidth as well as the power efficiency of high-activity data communication between memory and logic chips, over conventional planar bus structures on an FR-4 board or an interposer. The 3D stacking of memory chips advances memory systems in mobile applications as well as enabling low-cost high performance computation.
  Since it is not possible, within a 3D chip stack, to probe circuit nodes using physical needles or to magnify structures on silicon surfaces by optical or electron-beam microscopy, on-chip electronic diagnosis measures will only provide solutions to visualize internal signals on wires or to verify the operation of circuits. On the other hand, there is a need to observe analog waveforms on paths of signaling or in power delivery within a 3D stack, in order to characterize the propagation in vertical channels, unexpected weak opens in vertical connections, multi-tier background noise couplings, for example.
  In this paper, in-place waveform capture within a 3D chip stacking is proposed. A 3D chip stack featuring a 4096-bit wide I/O demonstrator is supplemented with an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms to diagnose circuits in the 3D integration. The collection of in-place waveforms on vertical channels with TSVs is demonstrated in 128 vertical I/O channels distributed in 8 banks in a 9.9 mm x 9.9 mm die area. The analog waveforms confirm a full 1.2 V swing of signaling at the maximum data transmission rate of 100 GByte/s with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/s, achieving the energy efficiency of 0.21 pJ/bit.
  The in-place waveform capturing functionality is highly useful in the in-depth characterization of electrical as well as mechanical properties of 3D integration, specifically, even with the assembly technologies currently under active development.