Best Paper Award 2013

Best Paper Award

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors’ Variation in SRAM Bitcells

Shunsuke Okumura , Shusuke Yoshimoto , Hiroshi Kawaguchi , Masahiko Yoshimoto

[Trans. Fundamentals., Vol. E95-A No.12, Dec. 2012 ]

Shunsuke Okumura

Shusuke Yoshimoto

Hiroshi Kawaguchi

Masahiko Yoshimoto

　For many applications, a unique identification (ID) on each chip is necessary to prevent illegal copying of copyrighted information. For instance, a radio frequency identification (RFID) tag and chip validation must have unique IDs. In conventional methods, chip IDs are provided by laser fuses or by writing data to ROM. However, these methods entail additional costs or fabrication processing. Recently, to address this issue, physical unclonable functions (PUFs) using inherent transistor variation have been proposed. The fingerprint generated by a PUF is unpredictable. Therefore, the PUFs cannot be reproduced using a manufacturing process. To identify a registered chip, a challenge-response pair (CRP) recorded in a database is referenced. In this paper, a fingerprint generating scheme using SRAM is proposed.
　In a conventional SRAM PUF, an initial value stored to bitcells at power-on is applied as a fingerprint. The data are determined by the Vth mismatches of the transistors comprising the bitcells. However, in the conventional scheme, it is difficult to initialize data of the bitcells after the device is initially powered on; the device can no longer generate a new fingerprint because of the long time taken by the power-on process to discharge the bitcells’ internal node voltages completely. This disadvantage precludes use of a fuzzy extractor, which improves the PUF’s reliability; it must measure responses many times to extract the most likely response. This paper proposes a chip ID generation scheme which realizes repeatable generations of fingerprints using SRAM. The proposed circuit is modified with a write driver and power switches in the SRAM. By controlling this additional circuit, a unique fingerprint is obtainable. The repeatability of the proposed scheme is better than that of the conventional scheme, and high identification probability is realized. Furthermore, the proposed scheme reduces power consumption compared with the conventional power-up scheme.
　As mentioned above, this paper proposes a chip identification generating scheme with random variation of transistor characteristics in SRAM bitcells which are applied to many ICs. The proposed scheme realizes low-power and high-reliability fingerprint generation with small area overhead. The authors’ contribution is highly regarded.