The Best Paper Award
Present and Future Processor Design Methodology -Design Flow and CAD System to Achieve Higher Performance -
Noriyuki ITO , Moritoshi YASUNAGA
(和文論文誌D 平成23年12月号掲載)
Noriyuki ITO Moritoshi YASUNAGA        
 This paper surveys 123 papers related to processors published since the late 90s and dealing with the topics of circuit design, design flow and CAD systems from various viewpoints. This paper is valuable not only for specialists but also for a wide range of researchers including students, in understanding the whole process of processor design.
 In this paper, many processors whose design methodologies including CAD systems have been published are surveyed such as Alpha, Cell, Cell Broadband, Itanium, Itanium2, POWER4, POWER6, SH-4, SPARC, SPARC V9, SPARC64, SX-9, S/390 G5/G6, UltraSPARC, UltraSPARC T1/T2, Xeon, x-86-64 core, zSeries and z900.
 Processor design consists of “architecture design,” “logic design,” “circuit design” and “physical design.” At each level of the design hierarchy, it is essential to understand both how to realize a CAD system and how to apply its design flow in order to realize high performance processors.
 Processor frequency, clock design, delay minimization, hierarchical design (size of blocks, border between logical and physical design), design flow, custom design and timing optimization are described in detail.
 With further semiconductor miniaturization, statistical design will become indispensable in replacing conventional deterministic design. In statistical design, it is important to be able to identify the parts of circuit which dominate the yield percentage of the processor. Moreover, we should consider the leakage current, which has 20 times dispersion in comparison with the dispersion of peak operating frequency, when designing high performance processors.
 Finally, the authors recommend the study of new approaches being adopted in world-wide processor design, because conventional CAD systems are unable to handle the increasing complication of processor design.
 As explained above, this paper is highly valued for its contribution in extending readers’ knowledge about present and future processor design methodologies.

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