| Leading Research on Scalable Wideband RF CMOS Integrated Circuits |
| Kazuya Masu , Noboru Ishihara |
 Kazuya Masu |
 Noboru Ishihara |
The awardees’ challenges have been to develop scalable wideband RF circuits and to establish their design methodologies. The concept is “implementing RF circuits using only CMOS inverters and switches”, which is derived from consideration of the analog characteristics of the digital circuits.
The features of the analog characteristics of digital circuits are: (i) an inductor-less approach leads to low power operation and smaller area; (ii) wideband operation can also be possible with an inductor-less technique; (iii) it is easy to achieve analog performance requirements, such as linearity and noise tolerance, because of the full amplitude operation from GND to power supply voltage (so-called rail-to-rail operation); and (iv) it is easy to provide an interface with a digital circuit and this is advantageous in implementing mixed RF and digital circuits.
（１） Amplifiers for RF transmitter and receiver circuits The following techniques have been developed: (a) a combination of the Cherry-Hooper structure and active feedback, which enables wider frequency band operation in an amplifier based on CMOS inverters [1] (Fig.2); (b) variable gain techniques by combination with MOS switches; and (c) a high-output power amplifier composed of cascaded stacked MOS transistors [2].
（２） Voltage controllable oscillators (VCO) and phase locked loop (PLL) circuits Although a ring-oscillator type VCO consisting of CMOS inverters has scalable features, it has not been applied to RF circuits so far because of its large phase noise. In order to overcome this problem, the awardees pioneered a low phase noise ring-oscillator-type VCO using a reference signal injection locking technique [3]. Furthermore, the design methodology of PLL circuits using a ring VCO has been clarified [4, 5].
Fig.1. Relation between CMOS technology and circuit performance and functionality.
Fig.2. Scalable wideband circuit with small chip area
Fig.3. Scalability trend of the CMOS inverter based LNA
The awardees’ pioneering work in these areas is highly appreciated because their results have been based on the design, fabrication and evaluation of CMOS integrated circuits using 180 nm, 90 nm, 65 nm, and 40 nm technologies.
Fig. 3 shows an example of the scalability trend of CMOS-inverter based wideband low noise amplifiers (LNA). These experimental results show that the proposed LNA has the feature of scalable characteristics. This kind of information on scalable characteristics is useful for the design of further miniaturized CMOS analog and RF circuits.
In these ways the awardees have faced the challenges of research on scalable wideband RF CMOS integrated circuits and produced many pioneering results for next-generation RF circuit techniques. The impact is that these technologies have a potential to replace conventional RF circuit techniques and are especially effective for implementing mixed analog digital LSIs (SoC).
Their work has been also summarized and published in invited papers [8-10]. It is also appreciated that during their work they have supervised many BS, MS, and Ph.D students and they have also made many presentations and publications in domestic and international conferences and journals. The achievements are quite outstanding and make the recipients eligible for the Achievement Award.
(２) H. Kiumarsi, Y. Mizuochi, H. Ito, N. Ishihara, and K. Masu, “A three-stage inverter-based stacked power amplifier in 65nm complementary metal oxide semiconductor process,” Jpn. J. Appl. Phys., vol.51, 02BC01, Feb. 2012.
(３) S. Lee, S. Amakawa, N. Ishihara, and K. Masu, “2.4-10GHz low-noise injection-locked ring voltage controlled oscillator in 90nm complementary metal oxide semiconductor,” Jpn. J. Appl. Phys., vol.50, 04DE03, April 2011.
(４) S. Lee, H. Ito, S. Amakawa, S. Tanoi, N. Ishihara, and K. Masu, “1.2-17.6GHz ring-oscillator-based phase-locked loop with injection locking in 65nm complementary metal oxide semiconductor,” Jpn. J. Appl. Phys., vol.51, 02BE03, Feb. 2012.
(５) S. Lee, S. Ikeda, H. Ito, S. Tanoi, N. Ishihara, and K. Masu, “An inductorless injection-locked PLL with 1/2-and 1/4-integral subharmonic locking in 90nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium 2012 (RFIC2012), Montreal, Canada, June 2012.
(６) K. Nakano, S. Amakawa, N. Ishihara, and K. Masu, “RF signal generator using time domain harmonic suppression technique in 90nm CMOS,” IEICE Electronics Express, vol.9, no.4, pp.270-275, Feb. 2012.
(７) A. Shirane, M. Otsuru, S. Lee, S. Yonezawa, S. Tanoi, H. Ito, N. Ishihara, and K. Masu, “A process-scalable RF transceiver for short range communication in 90nm Si CMOS,” IEEE Radio Frequency Integrated Circuits Symposium 2012 (RFIC2012), Montreal, Canada, June 2012.
(８) K. Masu, N. Ishihara, N. Nakayama, T. Sato, and S. Amakawa, “Physical design challenges to nano-CMOS circuits,” IEICE Electronics Express, vol.6, no.11, pp.703-720, June 2009 (Invited Paper).
(９) N. Ishihara, S. Amakawa, and K. Masu, “RF CMOS integrated circuit:History, current status and future prospects,” IEICE Trans. Fundamentals, Vol.E94-A, no.2, pp.556-567, Feb. 2011 (Invited Paper).
(10) K. Masu, S. Amakawa, H. Ito, N. Ishihara, “Challenges and Opportunities of RF CMOS in Wireless Communication”, The Journal of the IEICE, pp.427-432, Vol. 94, No. 5, 2011.(in Japanese)
