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DB info
Kazuto Nishimura, Masaki Hirota, Takafumi Terahara and Hideki Matsui,
"FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch,"
IEICE Tech. Rep., CS2019-5, pp. 25-30, April 2019.
Report Number: CS2019-5
pLaTeX format
The abbreviation of author's names was made automatically. Please confirm them before you cut and paste.
\bibitem{cs2019-5}
Kazuto~Nishimura, Masaki~Hirota, Takafumi~Terahara and Hideki~Matsui,
``FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch,''
{\em IEICE Tech. Rep.}, CS2019-5, pp.~25-30, April 2019.
Detailed information on the IEICE database
| Top & Workshop Schedule / Topics / Award / Submission / Photo / Committee / DB / Links |
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