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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Point Selection Method for Multi-Cycle BIST Using Deep Reinforcement Learning Kohei Shiotani, Tatsuya Nishikawa, Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)  DC2023-98 |
Multi-cycle BIST is a test method that performs multiple captures for each scan pattern, proving effective in reducing t... [more] | DC2023-98 pp.23-28 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:45 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Implementation Evaluation of a Memorism Pattern Matching Accelerator on FPGA Shion Honda, Tatsuya Nishikawa, Xihong Zhou, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Katsumi Inoue (AOT) VLD2023-61 ICD2023-69 DC2023-68 RECONF2023-64 |
[more] | VLD2023-61 ICD2023-69 DC2023-68 RECONF2023-64 pp.162-167 |
| DC | 2023-02-28 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
Test Point Selection Method Using Graph Neural Networks and Deep Reinforcement Learning Shaoqi Wei, Kohei Shiotani, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2022-87 |
It is well known that selecting the optimal test point to maximize the fault coverage is NP-hard. Conventional heuristic... [more] | DC2022-87 pp.27-32 |
| DC | 2021-02-05 14:25 |
Online | Online | Fault Coverage Estimation Method in Multi-Cycle Testing Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) DC2020-75 |
[more] | DC2020-75 pp.36-41 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 11:20 |
Online | Online | Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test Hikaru Tamaki, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34 |
[more] | VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34 pp.24-29 |
| DC | 2020-02-26 10:50 |
Tokyo | A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2019-88 |
[more] | DC2019-88 pp.13-18 |
|
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:10 |
Ehime | Ehime Prefecture Gender Equality Center | Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69 |
In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test (POST) is require... [more] |
VLD2019-45 DC2019-69 pp.145-150 |
| DC | 2019-02-27 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79 |
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] | DC2018-79 pp.49-54 |
| DC | 2018-02-20 16:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87 |
MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] | DC2017-87 pp.61-66 |
| SS, MSS | 2018-01-18 15:45 |
Hiroshima | Study on Deployment of a Computer Algebra System for Generating Random Test Patterns for Combinational Circuits Tsutomu Inamoto, Yoshinobu Higami (Ehime Univ.) MSS2017-57 SS2017-44 |
In this study, the authors display an attempt of deploying a computer algebra system to improve the fault detection rate... [more] | MSS2017-57 SS2017-44 pp.59-64 |
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| ASN | 2017-05-25 10:50 |
Tokyo | Tokyo Univ. (Institute of Industrial Science) | Multi-Platform Application to Report Marine Water Information for Prediction of Red Tide Occurrence Keiichi Endo, Kazuya Kusuno, Takuya Fujihashi, Hisayasu Kuroda, Yoshinobu Higami, Shinya Kobayashi (Ehime Univ.) ASN2017-3 |
A red tide is a serious problem in culture industry because of the death or quality degradation of cultured fish. In o... [more] |
ASN2017-3 pp.13-18 |
| DC | 2017-02-21 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Built-In Self Diagnosis Architecture for Logic Design Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Satoshi Ohtake (Oita Univ.) DC2016-76 |
Recently, roles of automotive LSI to realize a functional safety of vehicle are increasing. In order to guarantee the fu... [more] | DC2016-76 pp.11-16 |
| DC | 2016-02-17 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-88 |
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] | DC2015-88 pp.13-18 |
| DC | 2016-02-17 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Analog Circuit Design for a Precision Resistance Measurement of TSVs Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-94 |
[more] | DC2015-94 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 14:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-42 DC2015-38 |
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] | VLD2015-42 DC2015-38 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-65 DC2015-61 |
[more] | VLD2015-65 DC2015-61 pp.177-182 |
| MSS, CAS, IPSJ-AL [detail] | 2015-11-21 14:35 |
Kagoshima | Ibusuki CityHall | Preliminary Study on the Trip-based Integer Linear Programming Model for Static Multi-car Elevator Operation Problems Tsutomu Inamoto, Yoshinobu Higami (Ehime Univ.) CAS2015-60 MSS2015-34 |
In this study, we report some preliminary results to optimize operations for multi-car elevator systems. This study appr... [more] | CAS2015-60 MSS2015-34 pp.129-134 |
| DC | 2015-02-13 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Simulated Annealing based Low IR Drop Pattern Selection Method for Resistive Open Fault Diagnosis Senling Wang, Taiga Inoue, Hanan T.al-awadhi, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2014-87 |
[more] | DC2014-87 pp.55-60 |
| MSS | 2014-03-06 16:45 |
Ehime | Ehime Univ. | A Numerical Study on Optimality of Elevator Operations by a Zoning Technique Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi (Ehime Univ.) MSS2013-82 |
In this study, some preliminary results on optimality of elevator operations by a zoning technique are displayed. Thi... [more] |
MSS2013-82 pp.43-48 |
| DC | 2013-02-13 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] | DC2012-84 pp.25-30 |
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