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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-21
16:35		 Fukuoka Kitakyushu International Conference Center A low power consumption processor with on-chip control mechanism using pipeline stage unification
Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) RECONF2007-42		 In this paper, we implement and estimate the low power consumption processor which uses Pipeline Stage Unification (PSU)... [more] RECONF2007-42
pp.37-42
ICD, IPSJ-ARC 2007-05-31
11:00		 Kanagawa   A Study on Control Scheme of Awake Time in Drowsy Caches
Ryotaro Kobayashi, Hideki Taniguchi, Toshio Shimada (Nagoya Univ.) 		Recently static power due to the leakage current has been a major problem as process technology advances. Drowsy Cache ... [more] ICD2007-18
pp.7-12
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-17
13:50		 Kanagawa   An LSI design to support Sound Finite Difference Time Domain Method
Daichi Ito, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) 		Recently the FDTD method is used for sound field analysis because it can treat various structures and the procedure to o... [more] VLD2005-90 CPSY2005-46 RECONF2005-79
pp.13-18
CPSY, VLD, IPSJ-SLDM 2005-01-26
14:10		 Kanagawa   Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY
Akio Kamimurai, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada (Nagoya Univ.) 		We have proposed multi-processor architecture, called SKY, which efficiently executes multiple threads in parallel. In p... [more] VLD2004-117 CPSY2004-83
pp.43-48
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