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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 19 of 19  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
09:55
Online Online Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers
Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2021-50 CPSY2021-19 RECONF2021-58
In this study, we propose reverse converters for moduli set ${2^k,2^n+1,2^n-1}$ that convert residue number system to we... [more] VLD2021-50 CPSY2021-19 RECONF2021-58
pp.7-12
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-25
16:20
Online Online Residual signed-digit number - residual binary number conversion algorithm
Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-51 CPSY2020-34 RECONF2020-70
By applying SD(Signed-Digit) number representation, redundant residue number representation including negative number ca... [more] VLD2020-51 CPSY2020-34 RECONF2020-70
pp.69-74
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-25
17:35
Online Online High speed architectures of decimal counters
Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-54 CPSY2020-37 RECONF2020-73
In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed usin... [more] VLD2020-54 CPSY2020-37 RECONF2020-73
pp.85-89
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
10:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm
Masaki Ogino, Yuki Tanaka, Shugang Wei (Gunma Univ.) VLD2018-73 CPSY2018-83 RECONF2018-47
The modular multiplication inverse is used to generate the secret key of the public key cryptosystem from the difficulty... [more] VLD2018-73 CPSY2018-83 RECONF2018-47
pp.7-12
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
13:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set
Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2017-69 CPSY2017-113 RECONF2017-57
 [more] VLD2017-69 CPSY2017-113 RECONF2017-57
pp.43-48
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-24
17:20
Kanagawa Hiyoshi Campus, Keio Univ. A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption
Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2016-92 CPSY2016-128 RECONF2016-73
In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such a... [more] VLD2016-92 CPSY2016-128 RECONF2016-73
pp.147-152
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
10:30
Kanagawa Hiyoshi Campus, Keio University Error detection using residue signed-digit number arithmetic for arithmetic circuits
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] VLD2014-136 CPSY2014-145 RECONF2014-69
pp.151-156
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:10
Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68
Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]
VLD2012-114 CPSY2012-63 RECONF2012-68
pp.39-44
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
14:35
Kanagawa   Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69
RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the... [more] VLD2012-115 CPSY2012-64 RECONF2012-69
pp.45-50
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
10:50
Kanagawa Hiyoshi Campus, Keio University A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set
Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2011-110 CPSY2011-73 RECONF2011-69
In this paper, a residue-weighted number conversion algorithm using SD(signed-digit) arithmetic for a moduli set \{$2^n$... [more] VLD2011-110 CPSY2011-73 RECONF2011-69
pp.111-116
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
11:15
Kanagawa Hiyoshi Campus, Keio University Error Checker using Binary tree structure of Residue Signed-Digit Additions
Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2011-111 CPSY2011-74 RECONF2011-70
In this paper, a fast residue checker for error detection of arithmetic circuits is presented. The residue checker consi... [more] VLD2011-111 CPSY2011-74 RECONF2011-70
pp.117-121
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
15:45
Kanagawa Keio Univ (Hiyoshi Campus) Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation
Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2010-96 CPSY2010-51 RECONF2010-65
Residue arithmetic based on a radix-two signed-digit (SD) number system was proposed.Compared to the design of conventio... [more] VLD2010-96 CPSY2010-51 RECONF2010-65
pp.75-80
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
16:05
Kanagawa Keio Univ (Hiyoshi Campus) Audio dynamic range compression using polynomial equations
Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2010-97 CPSY2010-52 RECONF2010-66
An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating poly... [more] VLD2010-97 CPSY2010-52 RECONF2010-66
pp.81-85
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
15:55
Kanagawa Keio Univ (Hiyoshi Campus) Residue-Binary Conversion Using Signed-Digit Number Arithmetic
Changjun Jiang, Shugang Wei (Gunma Univ.) VLD2009-80 CPSY2009-62 RECONF2009-65
By introducing a signed-digit(SD) number arithmetic into a residue number system (RNS), arithmetic operations can be per... [more] VLD2009-80 CPSY2009-62 RECONF2009-65
pp.71-76
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
16:20
Kanagawa Keio Univ (Hiyoshi Campus) Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation
Mingda Zhang, Shugang Wei (Gunma Univ.) VLD2009-81 CPSY2009-63 RECONF2009-66
 [more] VLD2009-81 CPSY2009-63 RECONF2009-66
pp.77-82
DC 2009-02-16
11:30
Tokyo   Decimal adder using abacus architecture and its application to residue arithmetic
Tadahito Iijima, Shugang Wei (Gunma Univ.) DC2008-71
In a decimal number system, arithmetic circuits are implemented by using the binary number representations well known as... [more] DC2008-71
pp.19-23
CPM, ICD 2008-01-18
09:40
Tokyo Kikai-Shinko-Kaikan Bldg Arithmetic operation circuit based on abacus architecture
Syunsuke Nagasawa, Shugang Wei (Gunma Univ) CPM2007-137 ICD2007-148
In arithmetic circuits, the carrying propagation limits the
operation speed. To shorten the length of the carrying pr... [more]
CPM2007-137 ICD2007-148
pp.53-58
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-17
14:50
Tokyo Keio Univ. Hiyoshi Campus Design of Residue Dividers Using Signed-Digit Number Residue Addition
Peng Jia, Shugang Wei (Gunma Univ.)
(To be available after the conference date) [more] VLD2006-88 CPSY2006-59 RECONF2006-59
pp.19-24
CPSY, VLD, IPSJ-SLDM 2005-01-26
17:20
Kanagawa   Architecture of RNS to Mixed-Radix Number Converter Using Signed-Digit Number Arithmetic
Yumi Ogawa, Shuangching Chen, Shugang Wei (Gunma Univ.)
By introducing a signed-digit(SD) number arithmetic into a residue number system (RNS), arithmetic operations can be per... [more] VLD2004-123 CPSY2004-89
pp.79-84
 Results 1 - 19 of 19  /   
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