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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2012-03-06
13:10		 Oita B-con Plaza 10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control
Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) VLD2011-124		 For next-generation optical access systems, we developed a 10G/1G dual-rate EPON OLT LSI that fully conforms to the IEEE... [more] VLD2011-124
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-30
11:20		 Miyazaki NewWelCity Miyazaki 10G-EPON OLT and ONU LSIs for next-generation FTTx system
Tomoaki Kawamura, Shoko Ohteru, Sadayuki Yasuda, Akihiko Miyazaki, Kenji Kawai, Ritsu Kusaba, Mamoru Nakanishi, Masami Urano, Tsugumichi Shibata (NTT) CPM2011-167 ICD2011-99		 10G-EPON OLT and ONU LSIs that integrate the full functions confirming to the IEEE 802.3av standard were developed for n... [more] CPM2011-167 ICD2011-99
pp.97-102
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
10:45		 Fukuoka Kyushu University FPGA design and test methodology for communication frame processinng
Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT) VLD2010-67 DC2010-34		 For large-scale and high-speed frame processing on a ＦＰＧＡ board, we propose a new design method based on the property of... [more] VLD2010-67 DC2010-34
pp.73-78
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