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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICSS | 2017-11-20 15:15 |
Oita | Beppu International Convention Center | Preliminary Evaluation on the Program Classification at the Processor Level using Machine Learning Ryotaro Kobayashi (Kogakuin Univ.), Hayate Takase, Genki Otani, Ren Ohmura (Toyohashi Univ. of Tech.), Masahiko Kato (Univ. of Nagasaki)  ICSS2017-39 |
As use of IoT devices becomes widespread, a lot of things are connected to the Internet, and the convenience of everyday... [more] | ICSS2017-39 pp.5-10 |
| ICSS | 2016-11-25 15:20 |
Kanagawa | Institute of Information Security | Discussion and Evaluation on Regeneration of New Kyoto 2006+ Data Set Ryunosuke Tada, Ryotaro Kobayashi (Toyohashi Univ. of Tech.), Hajime Shimada (Nagoya Univ.), Hiroki Takakura (NII) ICSS2016-42 |
Network-based Intrusion Detection Systems (NIDSs) are used to counteract cyber-attacks, and thus various studies have be... [more] | ICSS2016-42 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 09:45 |
Kagoshima | Energy Reduction of BTB by focusing on Number of Branches per Cache Line Hiroki Yamamoto, Ryotaro Kobayashi (TUT), Hajime Shimada (NU) CPSY2014-177 DC2014-103 |
Recent processors exploit Instruction Level Parallelism to improve performance, but it's limited by control dependency. ... [more] | CPSY2014-177 DC2014-103 pp.89-94 |
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| CPSY | 2014-10-10 14:15 |
Chiba | Meeting Room 303, International Conference Hall, Makuhari-Messe | Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution Hajime Shimada (Nagoya Univ.), Ryotaro Kobayashi (Toyohashi Univ. of Tech.) CPSY2014-53 |
Recent many-core processor frequently utilizes 2-way in-order execution core which is diverted from high-performance em... [more] |
CPSY2014-53 pp.37-42 |
| CPSY | 2013-11-08 09:00 |
Hiroshima | Low Energy Consumption Oriented Heterogeneous Clustered Processor by Renewing A Part of Register Value Shoma Kawai, Ryotaro Kobayashi (Toyohashi Univ. of Tech.), Hajime Shimada (Nagoya Univ.) CPSY2013-39 |
Recently, as technology advances, microprocessor performance has increased. But, improving processor performance is caus... [more] | CPSY2013-39 pp.1-6 |
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| CPSY | 2013-11-08 09:20 |
Hiroshima | Evaluation of a Dependable Interrupt Interface by Bundled Interrupt Request Lines Hayato Nomura (Toyohashi Univ. of Tech.), Hajime Shimada (Nagoya Univ.), Ryotaro Kobayashi (Toyohashi Univ. of Tech.) CPSY2013-40 |
Conventional processors are exposed to not only on-chip transient faults caused by radiation and permanent failures due ... [more] | CPSY2013-40 pp.7-12 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 16:35 |
Fukuoka | Kitakyushu International Conference Center | A low power consumption processor with on-chip control mechanism using pipeline stage unification Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) RECONF2007-42 |
In this paper, we implement and estimate the low power consumption processor which uses Pipeline Stage Unification (PSU)... [more] | RECONF2007-42 pp.37-42 |
| ICD, IPSJ-ARC | 2007-05-31 11:00 |
Kanagawa | A Study on Control Scheme of Awake Time in Drowsy Caches Ryotaro Kobayashi, Hideki Taniguchi, Toshio Shimada (Nagoya Univ.) |
Recently static power due to the leakage current has been a major problem as process technology advances. Drowsy Cache ... [more] | ICD2007-18 pp.7-12 |
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| RECONF, CPSY, VLD, IPSJ-SLDM | 2006-01-17 13:50 |
Kanagawa | An LSI design to support Sound Finite Difference Time Domain Method Daichi Ito, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) |
Recently the FDTD method is used for sound field analysis because it can treat various structures and the procedure to o... [more] | VLD2005-90 CPSY2005-46 RECONF2005-79 pp.13-18 |
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| CPSY, VLD, IPSJ-SLDM | 2005-01-26 14:10 |
Kanagawa | Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY Akio Kamimurai, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada (Nagoya Univ.) |
We have proposed multi-processor architecture, called SKY, which efficiently executes multiple threads in parallel. In p... [more] | VLD2004-117 CPSY2004-83 pp.43-48 |
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