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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2019-09-19
14:00		 Fukuoka KITAKYUSHU Convention Center A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function
Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech) RECONF2019-21		 The placement of an FPGA design is performed using the simulated annealing algorithm with a cost function predicting wir... [more] RECONF2019-21
pp.3-8
NLP, CAS 2017-10-05
13:50		 Niigata Machinaka Campus Nagaoka Complete analysis of piecewise-linear resistive circuits using integer programming
Ryota Watanabe, Hiroki Takahara, Kiyotaka Yamamura (Chuo Univ.) CAS2017-26 NLP2017-51		 It is well-known that the geometry of the solution set of a piecewise-linear resistive circuit can be very complicated. ... [more] CAS2017-26 NLP2017-51
pp.11-16
ISEC, IT, WBS 2008-02-29
09:20		 Tokyo   Side Channel Attacks from Signal Lines of Cryptographic Modules -- Experiments for FPGA-Implemented AES --
Ryota Watanabe, Makoto Torikoshi, Yoshio Takahashi, Tsutomu Matsumoto (Yokohama National Univ.) IT2007-51 ISEC2007-148 WBS2007-82		  [more] IT2007-51 ISEC2007-148 WBS2007-82
pp.15-22
ICD, SDM 2006-08-18
10:15		 Hokkaido Hokkaido University Suppression effects of threshold voltage variation with Ni FUSI gate electrode for 45nm node and beyond LSTP and SRAM devices
Yasunori Okayama, Tomohiro Saito, Aname Oishi, Kazuaki Nakajima, Kouji Matsuo, Syuichi Taniguchi, Takatoshi Ono, Kazuhiro Nakayama, Ryota Watanabe, Ayumi Eiho, Taiki Komoda, Taiki Kimura, Mssahumi Hamaguchi, Yoichi Takekawa, Tomonori Aoyama (TOSHIBA) 		 [more] SDM2006-145 ICD2006-99
pp.115-120
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