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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-01 14:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Modeling of Thin-Film Ferroelectric Memcapacitors Based on Gaussian Process Regression and its evaluation Ryoga Urata (KIT), Taiyo Shinoda, Mutsumi Kimura (Ryukoku Univ.), Michihiro Shintani (KIT)  VLD2023-128 HWS2023-88 ICD2023-117 |
Ferroelectric memcapacitors using thin-film materials are attracting attention as a circuit element that can realize sum... [more] | VLD2023-128 HWS2023-88 ICD2023-117 pp.151-156 |
| MSS, CAS, SIP, VLD | 2023-07-06 10:40 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Autoencoder Based Incremental LSI Test Escape Detection Using Transfer Learning Ayano Takaya, Michihiro Shintani (KIT) CAS2023-4 VLD2023-4 SIP2023-20 MSS2023-4 |
Machine-learning-based test escape detection is gaining attention as a novel approach for detecting faulty large-scale i... [more] | CAS2023-4 VLD2023-4 SIP2023-20 MSS2023-4 pp.16-21 |
| MSS, CAS, SIP, VLD | 2023-07-06 11:00 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Lifetime improvement of Memristor-based Hyperdimensional Computing Inference Accelerator by Error Detection and Built-in Self Repair Tetsuro Iwasaki, Michihiro Shintani (KIT) CAS2023-5 VLD2023-5 SIP2023-21 MSS2023-5 |
The implementation of hyperdimensional computing in memristors is expected to realize a highly efficient inferencer for ... [more] | CAS2023-5 VLD2023-5 SIP2023-21 MSS2023-5 pp.22-27 |
| HWS, VLD | 2023-03-01 11:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test Daisuke Goeda (KIT), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michihiro Shintani (KIT) VLD2022-74 HWS2022-45 |
[more] | VLD2022-74 HWS2022-45 pp.7-12 |
| HWS, VLD | 2023-03-01 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process Yuta Shintani, Michiko Inoue (Naist), Michihiro Shintani (Kyoto Institute of Technology) VLD2022-75 HWS2022-46 |
There has been a great deal of research into the development of domain-specific circuits for multiply-and-accumulate pro... [more] | VLD2022-75 HWS2022-46 pp.13-18 |
| HWS, VLD | 2023-03-01 13:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT) VLD2022-76 HWS2022-47 |
Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vec... [more] | VLD2022-76 HWS2022-47 pp.19-24 |
| HWS, VLD | 2023-03-02 13:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects Takuma Nagao (NAIST), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing), Michiko Inoue (NAIST), Michihiro Shintani (Kyoto Institute of Technology) VLD2022-91 HWS2022-62 |
Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale inte... [more] | VLD2022-91 HWS2022-62 p.109 |
| VLD, HWS [detail] | 2022-03-08 09:55 |
Online | Online | Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology) VLD2021-92 HWS2021-69 |
Statistical methods for predicting the performance of large-scale integrated circuits (LSIs) manufactured on a wafer are... [more] | VLD2021-92 HWS2021-69 pp.87-92 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 14:20 |
Online | Online | Wafer-level Variation Modeling for Multi-site Testing of RF Circuits Riaz-ul-haque Mian (Shimane Univ.), Michihiro Shintani (NAIST) VLD2021-42 ICD2021-52 DC2021-48 RECONF2021-50 |
Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test q... [more] | VLD2021-42 ICD2021-52 DC2021-48 RECONF2021-50 pp.144-149 |
| SDM | 2021-11-11 11:00 |
Online | Online | [Invited Talk]
Non-Normal Model Parameter Generation for Variation-Aware Circuit Simulation Takashi Sato, Hiroki Tsukamoto, Song Bian (Kyoto Univ.), Michihiro Shintani (NAIST) SDM2021-54 |
[more] | SDM2021-54 pp.7-12 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 10:40 |
Online | Online | Unsupervised Recycled FPGA Detection Using Direct Density Ratio Estimation Based on Self-referencing Yuya Isaka (KGU), Michihiro Shintani (NAIST), Foisal Ahmed (PU), Michiko Inoue (NAIST) CPSY2020-60 DC2020-90 |
It is well known that the performance of field-programmable gate-array (FPGA) degrades over time due to their usage. Sev... [more] | CPSY2020-60 DC2020-90 pp.61-66 |
| HWS, VLD [detail] | 2020-03-05 10:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Fault-tolerant Design for Memristor Neural Network Using Checksum and Online Testing Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue (NAIST) VLD2019-112 HWS2019-85 |
[more] | VLD2019-112 HWS2019-85 pp.107-112 |
| DC | 2020-02-26 16:10 |
Tokyo | Accurate Recycled FPGA Detection Based on Exhaustive Path Analysis Michihiro Shintani, Foisal Ahmed, Michiko Inoue (NAIST) DC2019-96 |
[more] | DC2019-96 pp.61-66 |
|
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-13 10:55 |
Ehime | Ehime Prefecture Gender Equality Center | VLD2019-31 DC2019-55 |
In testing of large scale integration (LSI) circuit, test escape detection using machine learning algorithms has been at... [more] | VLD2019-31 DC2019-55 pp.13-18 |
| DC | 2019-02-27 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Variational Autoencoder-Based Efficient Test Escape Detection Michihiro Shintani (NAIST), Kouichi Kumaki (Renesas Electronics Corporation), Michiko Inoue (NAIST) DC2018-72 |
[more] | DC2018-72 pp.7-12 |
| DC | 2019-02-27 11:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling Foisal Ahmed, Michihiro Shintani, Michiko Inoue (NAIST) DC2018-77 |
Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their perfo... [more] | DC2018-77 pp.37-42 |
| HWS, VLD | 2019-02-28 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | A SPICE Model Parameter Extraction Environment Using Automatic Differentiation Aoi Ueda (NNCT), Michihiro Shintani (NAIST), Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT), Michiko Inoue (NAIST) VLD2018-117 HWS2018-80 |
Accuracy of circuit simulation highly relys on two techniques: compact modeling and parameter extraction. As increasing ... [more] | VLD2018-117 HWS2018-80 pp.145-150 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | VLD2018-50 DC2018-36 |
[more] | VLD2018-50 DC2018-36 pp.83-88 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2018-03-08 13:55 |
Shimane | Okinoshima Bunka-Kaikan Bldg. | CPSY2017-146 DC2017-102 |
Resistive RAM (ReRAM) is one of the most promising memory technologies due to its property such as high density, low-pow... [more] | CPSY2017-146 DC2017-102 pp.257-262 |
| DC | 2018-02-20 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue (NAIST), Alex Orailoglu (Univ. of California, San Diego) DC2017-84 |
High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through... [more] | DC2017-84 pp.43-48 |
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