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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, CAS | 2012-09-20 12:40 |
Kochi | Eikokuji Campus, University of Kochi | Desgin of a boot-strapped switch circuit to achieve continuous ON-state Naoaki Saimen, Masayoshi Tachibana (Kochi Univ of Tech)  CAS2012-30 NLP2012-56 |
This paper present that the desgin of a boot-strapped switch circuit to achieve continuous ON-state, the simulated of ... [more] |
CAS2012-30 NLP2012-56 pp.1-5 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:20 |
Kanagawa | A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79 |
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] | VLD2008-115 CPSY2008-77 RECONF2008-79 pp.141-146 |
|
| VLD, ICD | 2008-03-06 10:30 |
Okinawa | TiRuRu | Design and Evaluation of the component circuits for the PLL Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.) VLD2007-147 ICD2007-170 |
The PLL circuit consists of the phase detector, the loop filter, the voltage-controlled oscillator, and the divider. In ... [more] | VLD2007-147 ICD2007-170 pp.19-24 |
| VLD, ICD | 2008-03-06 12:00 |
Okinawa | TiRuRu | Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders Masayoshi Tachibana (kochi University of Technology) VLD2007-150 ICD2007-173 |
In this paper we address the area, delay and power consumption tradeoff for multiplier with tree-structured partial prod... [more] | VLD2007-150 ICD2007-173 pp.37-42 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-30 10:15 |
Fukuoka | Kitakyushu International Conference Center | Design of High Speed Multiplier with Tree-structured partial product adders Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) |
[more] | VLD2006-75 DC2006-62 pp.19-23 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-30 11:45 |
Fukuoka | Kitakyushu International Conference Center | Waveform measurment of LSI by using on-chip-probe Shinichi Kawagoe, Masayoshi Tachibana (KUT) |
[more] | VLD2006-78 DC2006-65 pp.37-41 |
| VLD, IPSJ-SLDM | 2006-05-12 13:30 |
Ehime | Ehime University | Delay and Power Consumption of Integer Multipiler
-- Comparison of Wallace and Dadda tree -- Masayoshi Tachibana (KUT) |
[more] | VLD2006-12 pp.37-40 |
| ICD, VLD | 2006-03-09 10:40 |
Okinawa | A hardware/software partitioning system with design navigation for system LSIs Yohei Kojima, Nozomu Togawa (Waseda Univ.), Masayoshi Tachibana (Kouchi Univ. of Technology), Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
[more] | VLD2005-111 ICD2005-228 pp.19-24 |
|
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 14:45 |
Fukuoka | Kitakyushu International Conference Center | Comparison of power consumption by form of adders Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) |
We reported "Comparison of power consumption, area and speed by form of adders " at the VLSI design technical research m... [more] | VLD2005-70 ICD2005-165 DC2005-47 pp.55-59 |
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