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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-02-29 16:45 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Tech)  VLD2023-119 HWS2023-79 ICD2023-108 |
(To be available after the conference date) [more] | VLD2023-119 HWS2023-79 ICD2023-108 pp.101-106 |
| RECONF | 2023-08-04 14:30 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Pianissimo: A Sub-mW Class DNN Accelerator For Adaptive Inference at Edge Junnosuke Suzuki, Mari Yasunaga, Angel Lopez Garcia-Arias, Yasuyuki Okoshi, Shungo Kumazawa (Tokyo Tech), Kota Ando (Hokkaido Univ.), Kazushi Kawamura, Thiem Van Chu, Masato Motomura (Tokyo Tech) RECONF2023-14 |
(To be available after the conference date) [more] | RECONF2023-14 pp.1-6 |
| NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] | 2023-06-29 13:55 |
Okinawa | OIST Conference Center (Primary: On-site, Secondary: Online) |
NC2023-2 IBISML2023-2 |
(To be available after the conference date) [more] | NC2023-2 IBISML2023-2 pp.9-16 |
| PRMU, IPSJ-CVIM | 2023-05-19 15:10 |
Aichi | (Primary: On-site, Secondary: Online) |
Ultralight Object Detection Neural Network based on Strong Lottery Ticket Hypothesis Hikari Otsuka, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura (Tokyo Tech) PRMU2023-11 |
[more] | PRMU2023-11 pp.57-61 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 15:15 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Study of Sparse Matrix Multiplication Accelerator Yuta Nagahara (Tokyo Tech), Kota Ando (Hokkaido University), Kazushi Kawamura, Jaehoon Yu, Masato Motomura, Thiem Van Chu (Tokyo Tech) CPSY2022-11 DC2022-11 |
[more] | CPSY2022-11 DC2022-11 pp.59-64 |
| SIS, IPSJ-AVM | 2021-06-24 13:25 |
Online | Online | A Study of Ensemble Learning for Randomly Weighted Neural Network Yasuyuki Okoshi, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu (Tokyo Tech) SIS2021-7 |
Recent research on deep learning shows the possibility of building neural networks by learning connection existences ins... [more] | SIS2021-7 pp.37-42 |
| RECONF | 2021-06-08 14:10 |
Online | Online | RECONF2021-2 |
(To be available after the conference date) [more] | RECONF2021-2 pp.2-7 |
| RECONF | 2021-06-08 15:00 |
Online | Online | RECONF2021-4 |
(To be available after the conference date) [more] | RECONF2021-4 pp.14-19 |
| RECONF | 2021-06-08 16:35 |
Online | Online | RECONF2021-7 |
(To be available after the conference date) [more] | RECONF2021-7 pp.32-37 |
| HWS, VLD [detail] | 2020-03-06 09:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
NA Sho Kanamaru, Kotaro Terada, Kazushi Kawamura, Shu Tanaka (Waseda Univ.), Yoshinori Tomita (Fujitsu Laboratories, Ltd), Nozomu Togawa (Waseda Univ.) VLD2019-124 HWS2019-97 |
[more] | VLD2019-124 HWS2019-97 pp.173-178 |
| VLD | 2017-03-01 15:55 |
Okinawa | Okinawa Seinen Kaikan | A Design Technique for Approximate Circuits based on Artificial Neural Network Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-106 |
This paper proposes a design technique for approximate circuits based on artificial neural network, and then evaluates t... [more] | VLD2016-106 pp.25-30 |
| VLD | 2016-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-120 |
In this paper, we evaluate the number of gates required for rotator-based MUX network including control circuits. Experi... [more] | VLD2015-120 pp.55-60 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 12:05 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-66 DC2015-62 |
The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, ... [more] | VLD2015-66 DC2015-62 pp.183-188 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita | B-ConPlaza | Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] | VLD2014-80 DC2014-34 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita | B-ConPlaza | A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.) VLD2014-101 DC2014-55 |
As seen in packet analysis of TCP/IP offload engine and stream data processing of encoder/decoder for video data, it is ... [more] | VLD2014-101 DC2014-55 pp.197-202 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 14:00 |
Hokkaido | Hokkaido University | A floorplan-driven high-level synthesis algorithm for reducing multiplexer inputs targeting FPGAs Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 |
[more] | CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 pp.219-224 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-61 DC2012-27 |
With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are ... [more] | VLD2012-61 DC2012-27 pp.13-18 |
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