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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY | 2013-10-03 11:35 |
Chiba | Makuhari Messe | A Chip Evaluation of Cube-1: A multi-core processor with 3D TCI Hideharu Amano, Yusuke Koizumi (Keio Univ.), Noriyuki Miura (Kobe Univ.), Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Agri. and Tech.), Kimiyoshi Usami, Masaaki Kondo (Univ. of Elect. Comm.), Hiroshi Nakamura (Univ. of Tokyo)  CPSY2013-33 |
[more] | CPSY2013-33 pp.13-18 |
| VLD, IPSJ-SLDM | 2013-05-16 14:10 |
Fukuoka | Kitakyushu International Conference Center | Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET Shohei Nakamura, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-5 |
Silicon on Thin Buried Oxide (SOTB) technology has an advantage that variation in threshold voltage can be more suppress... [more] | VLD2013-5 pp.43-48 |
| VLD | 2013-03-06 10:55 |
Okinawa | Okinawa Seinen Kaikan | Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155 |
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it i... [more] | VLD2012-155 pp.105-110 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 15:00 |
Kanagawa | Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-116 CPSY2012-65 RECONF2012-70 |
[more] | VLD2012-116 CPSY2012-65 RECONF2012-70 pp.51-56 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:00 |
Kanagawa | Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] | VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 17:00 |
Kanagawa | Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] | VLD2012-120 CPSY2012-69 RECONF2012-74 pp.75-80 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Analytical model of energy dissipation for comparing adder architectures Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46 |
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] | VLD2012-80 DC2012-46 pp.123-128 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48 |
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] | VLD2012-82 DC2012-48 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-98 DC2012-64 |
This paper describes fine-grain control to power gate function units using the charge up phenomenon of the virtual groun... [more] | VLD2012-98 DC2012-64 pp.225-230 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) VLD2012-99 DC2012-65 |
The ALU of the ProcessingElement at 65nm process was operated by the ultra-low voltage, and delay time and survey of pow... [more] | VLD2012-99 DC2012-65 pp.231-236 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| VLD | 2012-03-07 15:15 |
Oita | B-con Plaza | Power-Switch Drive-circuit generation for Ground-Bounce reduction using the Genetic-Programming Makoto Miyauchi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-142 |
Ground Bounce noise is a serious problem Power Gating technology. In this research, as compared with the Daisy Chain whi... [more] | VLD2011-142 pp.133-138 |
| VLD | 2012-03-07 16:05 |
Oita | B-con Plaza | Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-144 |
Power Gating (PG) is one of the technologies for reducing leakage energy. The effectiveness of leakage energy reduction ... [more] | VLD2011-144 pp.145-150 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-25 14:55 |
Kanagawa | Hiyoshi Campus, Keio University | Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.) VLD2011-99 CPSY2011-62 RECONF2011-58 |
We have proposed a multi-voltage variable-pipeline router in order to reduce power consumption ofNetwork-on-Chip (NoC). ... [more] | VLD2011-99 CPSY2011-62 RECONF2011-58 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki | NewWelCity Miyazaki | Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-90 DC2011-66 |
In fine-grain power gating which performs cell-by-cell power gating (PG) , energy overhead consumed at sleep-in and slee... [more] | VLD2011-90 DC2011-66 pp.221-226 |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| DC, CPSY (Joint) |
2011-07-29 09:00 |
Kagoshima | Reducing Leakage Power Consumption of Functional Units with Fine-grained Power Gating Weihan Wang (Keio Univ.), Yuya Ohta (Shibaura inst. of tech.), Lei Zhao (Keio Univ.), Yoshifumi Ishii (Keio univ.), Kimiyoshi Usami (Shibaura inst. of tech.), Hideharu Amano (Keio Univ.) CPSY2011-9 |
High speed power gating techniques are useful for reducing leakage power by functional units of CPU core. This paper pre... [more] | CPSY2011-9 pp.1-6 |
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| MSS, CAS, VLD, SIP | 2011-07-01 10:50 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | [Panel Discussion]
Toward new developments of System and Signal Processing Subsociety Nagisa Ishiura (Kwansei Gakuin Univ.), Mitsunori Makino (Chuo Univ.), Kimiyoshi Usami (Shibaura Institute of Technology), Isao Yamada (Tokyo Institute of Technology), Kunihiko Hiraishi (JAIST), Shingo Yamaguchi (Yamaguchi Univ.), Masaki Nakamura (Toyama Pref. Univ.) CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 |
[more] | CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 p.127 |
| IPSJ-SLDM, VLD | 2011-05-18 15:45 |
Fukuoka | Kitakyushu International Conference Center | [Invited Talk]
Recent Gating-Techniques for Power Reduction Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2011-4 |
Key techniques to reduce power dissipation of LSIs are clock gating and power gating. In this talk, I will describe basi... [more] | VLD2011-4 pp.19-24 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
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